/**
 @file sys_at_serdes.h

 @author  Copyright (C) 2021 Centec Networks Inc.  All rights reserved.

 @date 2021-03-10

 @version v2.0

*/

#ifndef _SYS_AT_SERDES_H
#define _SYS_AT_SERDES_H
#ifdef __cplusplus
extern "C" {
#endif


enum sys_at_serdes_type_s
{
    SYS_AT_SERDES_56G = 0,
    SYS_AT_SERDES_112G,
    SYS_AT_SERDES_TYPE_MAX,
};
typedef enum sys_at_serdes_type_s sys_at_serdes_type_t;

/*112G macro define start*/

#define F_AT112G_PHY_MODE        AT_SERDES_FLD_DEF(0xA424, 14, 12)
#define F_AT112G_PHY_GEN_TX      AT_SERDES_FLD_DEF(0x5530, 17, 8)
#define F_AT112G_PHY_GEN_RX      AT_SERDES_FLD_DEF(0x5624, 17, 8)
#define F_AT112G_REF_FREF_SEL_TX AT_SERDES_FLD_DEF(0x5538, 31, 24)
#define F_AT112G_REF_FREF_SEL_RX AT_SERDES_FLD_DEF(0x5630, 7, 0)
#define F_AT112G_REFCLK_SEL_TX   AT_SERDES_FLD_DEF(0x5538, 22, 22)
#define F_AT112G_REFCLK_SEL_RX   AT_SERDES_FLD_DEF(0x5634, 30, 30)
#define F_AT112G_TX_SEL_BITS     AT_SERDES_FLD_DEF(0x3034, 31, 31)
#define F_AT112G_RX_SEL_BITS     AT_SERDES_FLD_DEF(0x3204, 31, 31)
#define F_AT112G_TXD_INV         AT_SERDES_FLD_DEF(0x3024, 30, 30)
#define F_AT112G_RXD_INV         AT_SERDES_FLD_DEF(0x3248, 29, 29)
#define F_AT112G_ANA_TX2RX_LPBK  AT_SERDES_FLD_DEF(0x1014, 3, 3)      /* LOCAL_ANA_TX2RX_LPBK_EN_LANE */
#define F_AT112G_DIG_RX2TX_LPBK  AT_SERDES_FLD_DEF(0x3024, 31, 31)    /* LOCAL_DIG_RX2TX_LPBK_EN_LANE */
#define F_AT112G_DIG_TX2RX_LPBK  AT_SERDES_FLD_DEF(0x3248, 31, 31)    /* LOCAL_DIG_TX2RX_LPBK_EN_LANE */
#define F_AT112G_RX_TRAIN_ENA    AT_SERDES_FLD_DEF(0x5630, 22, 22)    /* RX_TRAIN_ENABLE_LANE */
#define F_AT112G_RX_TRAIN_COM    AT_SERDES_FLD_DEF(0x5020, 4, 4)      /* RX_TRAIN_COMPLETE_LANE */
#define F_AT112G_RX_TRAIN_FAI    AT_SERDES_FLD_DEF(0x5020, 3, 3)      /* RX_TRAIN_FAILED_LANE */
#define F_AT112G_TX_TRAIN_ENA    AT_SERDES_FLD_DEF(0x5630, 20, 20)    /* TX_TRAIN_ENABLE_LANE */
#define F_AT112G_TX_TRAIN_COM    AT_SERDES_FLD_DEF(0x5020, 6, 6)      /* TX_TRAIN_COMPLETE_LANE */
#define F_AT112G_TX_TRAIN_FAI    AT_SERDES_FLD_DEF(0x5020, 5, 5)      /* TX_TRAIN_FAILED_LANE */
#define F_AT112G_TRX_TIMER       AT_SERDES_FLD_DEF(0x5018, 31, 16)    /* TRX_TRAIN_TIMER_LANE */
#define F_AT112G_RX_TIMER        AT_SERDES_FLD_DEF(0x5018, 15, 0)     /* RX_TRAIN_TIMER_LANE */
#define F_AT112G_TRX_TIMEOUT_EN  AT_SERDES_FLD_DEF(0x5014, 10, 10)    /* TRX_TRAIN_TIMEOUT_EN_LANE */
#define F_AT112G_TX_PHYREADY     AT_SERDES_FLD_DEF(0x3098, 30, 30)    /* PT_TX_PHYREADY_FORCE_LANE */
#define F_AT112G_RX_PHYREADY     AT_SERDES_FLD_DEF(0x3264, 22, 22)    /* PT_RX_PHYREADY_FORCE_LANE */
#define F_AT112G_TX_EN_MODE      AT_SERDES_FLD_DEF(0x3098, 3, 2)      /* PT_TX_EN_MODE_LANE */
#define F_AT112G_RX_EN_MODE      AT_SERDES_FLD_DEF(0x3264, 31, 30)    /* PT_RX_EN_MODE_LANE */
#define F_AT112G_TX_EN           AT_SERDES_FLD_DEF(0x3098, 31, 31)    /* PT_TX_EN_LANE */
#define F_AT112G_RX_EN           AT_SERDES_FLD_DEF(0x3264, 23, 23)    /* PT_RX_EN_LANE */
#define F_AT112G_TX_RST          AT_SERDES_FLD_DEF(0x3098, 5, 5)      /* PT_TX_RST_LANE */
#define F_AT112G_RX_RST          AT_SERDES_FLD_DEF(0x3270, 7, 7)      /* PT_RX_RST_LANE */
#define F_AT112G_TX_FIR_C0       AT_SERDES_FLD_DEF(0x30C8, 29, 24)
#define F_AT112G_TX_FIR_C0_F     AT_SERDES_FLD_DEF(0x30C8, 30, 30)    /* TX_FIR_C0_FORCE_LANE */
#define F_AT112G_TX_FIR_C1       AT_SERDES_FLD_DEF(0x30C8, 22, 17)
#define F_AT112G_TX_FIR_C1_F     AT_SERDES_FLD_DEF(0x30C8, 23, 23)    /* TX_FIR_C1_FORCE_LANE */
#define F_AT112G_TX_FIR_C2       AT_SERDES_FLD_DEF(0x30C8, 14, 9)
#define F_AT112G_TX_FIR_C2_F     AT_SERDES_FLD_DEF(0x30C8, 15, 15)    /* TX_FIR_C2_FORCE_LANE */
#define F_AT112G_TX_FIR_C3       AT_SERDES_FLD_DEF(0x30C8, 6, 1)
#define F_AT112G_TX_FIR_C3_F     AT_SERDES_FLD_DEF(0x30C8, 7, 7)      /* TX_FIR_C3_FORCE_LANE */
#define F_AT112G_TX_FIR_C4       AT_SERDES_FLD_DEF(0x30CC, 30, 25)
#define F_AT112G_TX_FIR_C4_F     AT_SERDES_FLD_DEF(0x30CC, 31, 31)    /* TX_FIR_C4_FORCE_LANE */
#define F_AT112G_TX_FIR_C5       AT_SERDES_FLD_DEF(0x30CC, 22, 17)
#define F_AT112G_TX_FIR_C5_F     AT_SERDES_FLD_DEF(0x30CC, 23, 23)    /* TX_FIR_C5_FORCE_LANE */
#define F_AT112G_TX_FIR_UPDATE   AT_SERDES_FLD_DEF(0x30CC, 8, 8)
#define F_AT112G_TX_FIR_UPDATE_F AT_SERDES_FLD_DEF(0x30CC, 7, 7)      /* TX_FIR_UPDATE_FORCE_LANE */
#define F_AT112G_ANA_TX_FIR_C0   AT_SERDES_FLD_DEF(0x30D0, 29, 24)    /* TO_ANA_TX_FIR_C0_LANE */
#define F_AT112G_ANA_TX_FIR_C1   AT_SERDES_FLD_DEF(0x30D0, 21, 16)    /* TO_ANA_TX_FIR_C1_LANE */
#define F_AT112G_ANA_TX_FIR_C2   AT_SERDES_FLD_DEF(0x30D0, 13, 8)     /* TO_ANA_TX_FIR_C2_LANE */
#define F_AT112G_ANA_TX_FIR_C3   AT_SERDES_FLD_DEF(0x30D0, 5, 0)      /* TO_ANA_TX_FIR_C3_LANE */
#define F_AT112G_ANA_TX_FIR_C4   AT_SERDES_FLD_DEF(0x30D4, 29, 24)    /* TO_ANA_TX_FIR_C4_LANE */
#define F_AT112G_ANA_TX_FIR_C5   AT_SERDES_FLD_DEF(0x30D4, 21, 16)    /* TO_ANA_TX_FIR_C5_LANE */
#define F_AT112G_ANA_TX_FIR_POL  AT_SERDES_FLD_DEF(0x30D4, 13, 8)     /* TO_ANA_TX_FIR_POL_LANE */
#define F_AT112G_TX_FIR_POL_F    AT_SERDES_FLD_DEF(0x30CC, 0, 0)      /* TX_FIR_TAP_POL_F_LANE */
#define F_AT112G_TX_FIR_POL      AT_SERDES_FLD_DEF(0x30CC, 6, 1)      /* TX_FIR_TAP_POL_LANE */
#define F_AT112G_TRAIN_CTLE_R    AT_SERDES_FLD_DEF(0x6378, 20, 16)    /* RX_TRAIN_CTLE_R_LANE */
#define F_AT112G_TRAIN_CTLE_C    AT_SERDES_FLD_DEF(0x6378, 15, 8)     /* RX_TRAIN_CTLE_C_LANE */
#define F_AT112G_TRAIN_CTLE_GC   AT_SERDES_FLD_DEF(0x6378, 4, 0)      /* RX_TRAIN_CTLE_GC_LANE */
#define F_AT112G_KP_FRAC         AT_SERDES_FLD_DEF(0x4A0C, 30, 29)    /* RX_DTL_LPF_KP_FRAC_LANE */
#define F_AT112G_KP_SHIFT        AT_SERDES_FLD_DEF(0x4A0C, 28, 25)    /* RX_DTL_LPF_KP_SHIFT_LANE */
#define F_AT112G_KI_SHIFT        AT_SERDES_FLD_DEF(0x4A0C, 23, 19)    /* RX_DTL_LPF_KI_SHIFT_LANE */
#define F_AT112G_KI_FRAC         AT_SERDES_FLD_DEF(0x4A0C, 17, 17)    /* RX_DTL_LPF_KI_FRAC_LANE */
#define F_AT112G_TX_PATTERN_SEL  AT_SERDES_FLD_DEF(0x3098, 29, 24)    /* PT_TX_PATTERN_SEL_LANE */
#define F_AT112G_RX_PATTERN_SEL  AT_SERDES_FLD_DEF(0x3264, 29, 24)    /* PT_RX_PATTERN_SEL_LANE */
#define F_AT112G_TXDATA_PRE_EN   AT_SERDES_FLD_DEF(0x5538, 18, 18)    /* TXDATA_PRE_CODE_EN_LANE */
#define F_AT112G_TX_UP_79_48     AT_SERDES_FLD_DEF(0x309C, 31, 0)     /* PT_TX_USER_PATTERN_LANE[79:48] */
#define F_AT112G_TX_UP_47_16     AT_SERDES_FLD_DEF(0x30A0, 31, 0)     /* PT_TX_USER_PATTERN_LANE[47:16] */
#define F_AT112G_TX_UP_15_0      AT_SERDES_FLD_DEF(0x30A4, 31, 16)    /* PT_TX_USER_PATTERN_LANE[15:0] */
#define F_AT112G_RXDATA_PRE_EN   AT_SERDES_FLD_DEF(0x5634, 26, 26)    /* RXDATA_PRE_CODE_EN_LANE */
#define F_AT112G_RX_UP_79_48     AT_SERDES_FLD_DEF(0x3268, 31, 0)     /* PT_RX_USER_PATTERN_LANE[79:48] */
#define F_AT112G_RX_UP_47_16     AT_SERDES_FLD_DEF(0x326C, 31, 0)     /* PT_RX_USER_PATTERN_LANE[47:16] */
#define F_AT112G_RX_UP_15_0      AT_SERDES_FLD_DEF(0x3270, 31, 16)    /* PT_RX_USER_PATTERN_LANE[15:0] */
#define F_AT112G_TXDATA_GRAY_EN  AT_SERDES_FLD_DEF(0x5538, 20, 20)    /* TXDATA_GRAY_CODE_EN_LANE */
#define F_AT112G_RXDATA_GRAY_EN  AT_SERDES_FLD_DEF(0x5634, 28, 28)    /* RXDATA_GRAY_CODE_EN_LANE */
#define F_AT112G_TXD_SWAP        AT_SERDES_FLD_DEF(0x3024, 18, 18)    /* TXD_MSB_LSB_SWAP_LANE */
#define F_AT112G_TXDATA_SWAP     AT_SERDES_FLD_DEF(0x3024, 5, 5)      /* TXDATA_MSB_LSB_SWAP_LANE */
#define F_AT112G_RXD_SWAP        AT_SERDES_FLD_DEF(0x3248, 28, 28)    /* RXD_MSB_LSB_SWAP_LANE */
#define F_AT112G_RXDATA_SWAP     AT_SERDES_FLD_DEF(0x3248, 25, 25)    /* RXDATA_MSB_LSB_SWAP_LANE */
#define F_AT112G_RX_LOCK         AT_SERDES_FLD_DEF(0x3270, 0, 0)      /* PT_RX_LOCK_LANE */
#define F_AT112G_RX_PASS         AT_SERDES_FLD_DEF(0x3270, 1, 1)      /* PT_RX_PASS_LANE */
#define F_AT112G_RX_CNT_47_32    AT_SERDES_FLD_DEF(0x3274, 31, 16)    /* PT_RX_CNT_LANE[47:32] */
#define F_AT112G_RX_CNT_31_0     AT_SERDES_FLD_DEF(0x3278, 31, 0)     /* PT_RX_CNT_LANE[31:0] */
#define F_AT112G_RX_ERR_47_32    AT_SERDES_FLD_DEF(0x327C, 31, 16)    /* PT_RX_ERR_CNT_LANE[47:32] */
#define F_AT112G_RX_ERR_31_0     AT_SERDES_FLD_DEF(0x3280, 31, 0)     /* PT_RX_ERR_CNT_LANE[31:0] */
#define F_AT112G_ESM_EN          AT_SERDES_FLD_DEF(0x6054, 18, 18)
#define F_AT112G_EOM_READY       AT_SERDES_FLD_DEF(0x6110, 8, 8)
#define F_AT112G_ESM_VOLTAGE     AT_SERDES_FLD_DEF(0x6110, 7, 0)
#define F_AT112G_ESM_PHASE       AT_SERDES_FLD_DEF(0x6054, 9, 0)
#define F_AT112G_EOM_CALL_CONV   AT_SERDES_FLD_DEF(0x6110, 9, 9)
#define F_AT112G_EOM_CALL        AT_SERDES_FLD_DEF(0x6110, 10, 10)
#define F_AT112G_EOM_D00_CNT     AT_SERDES_FLD_DEF(0x4590, 31, 0)     /* EOM_HIST_D00_CNT_LANE */
#define F_AT112G_EOM_D01_CNT     AT_SERDES_FLD_DEF(0x4594, 31, 0)     /* EOM_HIST_D01_CNT_LANE */
#define F_AT112G_EOM_D10_CNT     AT_SERDES_FLD_DEF(0x4598, 31, 0)     /* EOM_HIST_D10_CNT_LANE */
#define F_AT112G_EOM_D11_CNT     AT_SERDES_FLD_DEF(0x459C, 31, 0)     /* EOM_HIST_D11_CNT_LANE */
#define F_AT112G_EOM_N_D00_CNT   AT_SERDES_FLD_DEF(0x60B8, 31, 0)     /* EOM_HIST_N_D00_CNT_LANE */
#define F_AT112G_EOM_N_D01_CNT   AT_SERDES_FLD_DEF(0x60BC, 31, 0)     /* EOM_HIST_N_D01_CNT_LANE */
#define F_AT112G_EOM_N_D10_CNT   AT_SERDES_FLD_DEF(0x60C0, 31, 0)     /* EOM_HIST_N_D10_CNT_LANE */
#define F_AT112G_EOM_N_D11_CNT   AT_SERDES_FLD_DEF(0x60C4, 31, 0)     /* EOM_HIST_N_D11_CNT_LANE */
#define F_AT112G_EOM_BOT_H_CNT   AT_SERDES_FLD_DEF(0x4574, 31, 0)     /* EOM_HIST_BOT_H_CNT_LANE */
#define F_AT112G_EOM_BOT_L_CNT   AT_SERDES_FLD_DEF(0x4578, 31, 0)     /* EOM_HIST_BOT_L_CNT_LANE */
#define F_AT112G_EOM_MID_H_CNT   AT_SERDES_FLD_DEF(0x4580, 31, 0)     /* EOM_HIST_MID_H_CNT_LANE */
#define F_AT112G_EOM_MID_L_CNT   AT_SERDES_FLD_DEF(0x4584, 31, 0)     /* EOM_HIST_MID_L_CNT_LANE */
#define F_AT112G_EOM_TOP_H_CNT   AT_SERDES_FLD_DEF(0x4588, 31, 0)     /* EOM_HIST_TOP_H_CNT_LANE */
#define F_AT112G_EOM_TOP_L_CNT   AT_SERDES_FLD_DEF(0x458C, 31, 0)     /* EOM_HIST_TOP_L_CNT_LANE */
#define F_AT112G_EOM_N_BOT_H_CNT AT_SERDES_FLD_DEF(0x60A0, 31, 0)     /* EOM_HIST_N_BOT_H_CNT_LANE */
#define F_AT112G_EOM_N_BOT_L_CNT AT_SERDES_FLD_DEF(0x60A4, 31, 0)     /* EOM_HIST_N_BOT_L_CNT_LANE */
#define F_AT112G_EOM_N_MID_H_CNT AT_SERDES_FLD_DEF(0x60A8, 31, 0)     /* EOM_HIST_N_MID_H_CNT_LANE */
#define F_AT112G_EOM_N_MID_L_CNT AT_SERDES_FLD_DEF(0x60AC, 31, 0)     /* EOM_HIST_N_MID_L_CNT_LANE */
#define F_AT112G_EOM_N_TOP_H_CNT AT_SERDES_FLD_DEF(0x60B0, 31, 0)     /* EOM_HIST_N_TOP_H_CNT_LANE */
#define F_AT112G_EOM_N_TOP_L_CNT AT_SERDES_FLD_DEF(0x60B4, 31, 0)     /* EOM_HIST_N_TOP_L_CNT_LANE */
#define F_AT112G_RX_DATA_WIDTH   AT_SERDES_FLD_DEF(0x323C, 2, 1)
#define F_AT112G_DP_PRE6         AT_SERDES_FLD_DEF(0x4860, 2, 0)      /* RX_DP_LMS_FFE_PRE6_COE_LANE */
#define F_AT112G_DP_PRE5         AT_SERDES_FLD_DEF(0x485C, 2, 0)      /* RX_DP_LMS_FFE_PRE5_COE_LANE */
#define F_AT112G_DP_PRE4         AT_SERDES_FLD_DEF(0x4858, 4, 0)      /* RX_DP_LMS_FFE_PRE4_COE_LANE */
#define F_AT112G_DP_PRE3         AT_SERDES_FLD_DEF(0x4854, 4, 0)      /* RX_DP_LMS_FFE_PRE3_COE_LANE */
#define F_AT112G_DP_PRE2         AT_SERDES_FLD_DEF(0x4850, 5, 0)      /* RX_DP_LMS_FFE_PRE2_COE_LANE */
#define F_AT112G_DP_PRE1         AT_SERDES_FLD_DEF(0x484C, 6, 0)      /* RX_DP_LMS_FFE_PRE1_COE_LANE */
#define F_AT112G_DP_PST1         AT_SERDES_FLD_DEF(0x486C, 6, 0)      /* RX_DP_LMS_FFE_PST1_COE_LANE */
#define F_AT112G_DP_PST2         AT_SERDES_FLD_DEF(0x4870, 5, 0)      /* RX_DP_LMS_FFE_PST2_COE_LANE */
#define F_AT112G_DP_PST3         AT_SERDES_FLD_DEF(0x4874, 4, 0)      /* RX_DP_LMS_FFE_PST3_COE_LANE */
#define F_AT112G_DP_PST4         AT_SERDES_FLD_DEF(0x4878, 4, 0)      /* RX_DP_LMS_FFE_PST4_COE_LANE */
#define F_AT112G_DP_PST5         AT_SERDES_FLD_DEF(0x487C, 4, 0)      /* RX_DP_LMS_FFE_PST5_COE_LANE */
#define F_AT112G_DP_PST6         AT_SERDES_FLD_DEF(0x4880, 4, 0)      /* RX_DP_LMS_FFE_PST6_COE_LANE */
#define F_AT112G_DP_PST7         AT_SERDES_FLD_DEF(0x4884, 3, 0)      /* RX_DP_LMS_FFE_PST7_COE_LANE */
#define F_AT112G_DP_PST8         AT_SERDES_FLD_DEF(0x4888, 3, 0)      /* RX_DP_LMS_FFE_PST8_COE_LANE */
#define F_AT112G_DP_PST9         AT_SERDES_FLD_DEF(0x488C, 2, 0)      /* RX_DP_LMS_FFE_PST9_COE_LANE */
#define F_AT112G_DP_PST10        AT_SERDES_FLD_DEF(0x4890, 2, 0)      /* RX_DP_LMS_FFE_PST10_COE_LANE */
#define F_AT112G_DP_PST11        AT_SERDES_FLD_DEF(0x4894, 2, 0)      /* RX_DP_LMS_FFE_PST11_COE_LANE */
#define F_AT112G_DP_PST12        AT_SERDES_FLD_DEF(0x4898, 2, 0)      /* RX_DP_LMS_FFE_PST12_COE_LANE */
#define F_AT112G_DP_PST13        AT_SERDES_FLD_DEF(0x489C, 2, 0)      /* RX_DP_LMS_FFE_PST13_COE_LANE */
#define F_AT112G_DP_PST14        AT_SERDES_FLD_DEF(0x48A0, 2, 0)      /* RX_DP_LMS_FFE_PST14_COE_LANE */
#define F_AT112G_DP_PST15        AT_SERDES_FLD_DEF(0x48A4, 2, 0)      /* RX_DP_LMS_FFE_PST15_COE_LANE */
#define F_AT112G_DP_PST16        AT_SERDES_FLD_DEF(0x48A8, 2, 0)      /* RX_DP_LMS_FFE_PST16_COE_LANE */
#define F_AT112G_DP_GAIN         AT_SERDES_FLD_DEF(0x48E0, 10, 0)     /* RX_DP_LMS_GAIN_COE_LANE */
#define F_AT112G_DP_BLW          AT_SERDES_FLD_DEF(0x4810, 5, 0)      /* RX_DP_LMS_BLW_COE_LANE */
#define F_AT112G_DP_DFE          AT_SERDES_FLD_DEF(0x48E8, 5, 0)      /* RX_DP_LMS_DFE_COE_LANE */
#define F_AT112G_DTL_PRE3        AT_SERDES_FLD_DEF(0x4A4C, 3, 0)      /* RX_DTL_LMS_FFE_PRE3_COE_LANE */
#define F_AT112G_DTL_PRE2        AT_SERDES_FLD_DEF(0x4A48, 4, 0)      /* RX_DTL_LMS_FFE_PRE2_COE_LANE */
#define F_AT112G_DTL_PRE1        AT_SERDES_FLD_DEF(0x4A44, 5, 0)      /* RX_DTL_LMS_FFE_PRE1_COE_LANE */
#define F_AT112G_DTL_PST1        AT_SERDES_FLD_DEF(0x4A50, 5, 0)      /* RX_DTL_LMS_FFE_PST1_COE_LANE */
#define F_AT112G_DTL_PST2        AT_SERDES_FLD_DEF(0x4A54, 4, 0)      /* RX_DTL_LMS_FFE_PST2_COE_LANE */
#define F_AT112G_DTL_PST3        AT_SERDES_FLD_DEF(0x4A58, 3, 0)      /* RX_DTL_LMS_FFE_PST3_COE_LANE */
#define F_AT112G_DTL_GAIN        AT_SERDES_FLD_DEF(0x4A40, 9, 0)      /* RX_DTL_LMS_GAIN_COE_LANE */
#define F_AT112G_DTL_BLW         AT_SERDES_FLD_DEF(0x4A38, 4, 0)      /* RX_DTL_LMS_BLW_COE_LANE */
#define F_AT112G_AVDD_SEL        AT_SERDES_FLD_DEF(0xA420, 28, 26)
#define F_AT112G_SPD_CFG         AT_SERDES_FLD_DEF(0xA424, 7, 4)
#define F_AT112G_LANE_SEL        AT_SERDES_FLD_DEF(0xA318, 31, 28)
#define F_AT112G_FW_MAJOR_VER    AT_SERDES_FLD_DEF(0xE600, 31, 24)
#define F_AT112G_FW_MINOR_VER    AT_SERDES_FLD_DEF(0xE600, 23, 16)
#define F_AT112G_FW_PATCH_VER    AT_SERDES_FLD_DEF(0xE600, 15, 8)
#define F_AT112G_FW_BUILD_VER    AT_SERDES_FLD_DEF(0xE600, 7, 0)
#define F_AT112G_PLL_TS_LOCK_RD  AT_SERDES_FLD_DEF(0x5700, 6, 6)      /* ANA_PLL_TS_LOCK_RD_LANE */
#define F_AT112G_PLL_RS_LOCK_RD  AT_SERDES_FLD_DEF(0x5800, 30, 30)    /* ANA_PLL_RS_LOCK_RD_LANE */
#define F_AT112G_PLL_READY_TX    AT_SERDES_FLD_DEF(0x3000, 20, 20)
#define F_AT112G_PLL_READY_RX    AT_SERDES_FLD_DEF(0x3200, 24, 24)
#define F_AT112G_RX_INIT         AT_SERDES_FLD_DEF(0x5630, 24, 24)
#define F_AT112G_RX_INIT_DONE    AT_SERDES_FLD_DEF(0x3200, 19, 19)
#define F_AT112G_RX_CDR_LOCK     AT_SERDES_FLD_DEF(0x4A00, 10, 10)
#define F_AT112G_BROADCAST       AT_SERDES_FLD_DEF(0xA318, 27, 27)
#define F_AT112G_PU_PLL          AT_SERDES_FLD_DEF(0x5530, 6, 6)
#define F_AT112G_PU_TX           AT_SERDES_FLD_DEF(0x5530, 4, 4)
#define F_AT112G_PU_RX           AT_SERDES_FLD_DEF(0x5624, 6, 6)
#define F_AT112G_MCU_FREQ        AT_SERDES_FLD_DEF(0xA420, 15, 0)
#define F_AT112G_TX_IDLE         AT_SERDES_FLD_DEF(0x3014, 18, 18)
#define F_AT112G_PU_IVREF        AT_SERDES_FLD_DEF(0xA424, 2, 2)
#define F_AT112G_PU_IVREF_FM_REG AT_SERDES_FLD_DEF(0xA424, 1, 1)
#define F_AT112G_SQ_RES_RD       AT_SERDES_FLD_DEF(0x181C, 6, 1)      /* SQ_CAL_RESULT_RD_LANE */
#define F_AT112G_SQ_RES_EXT      AT_SERDES_FLD_DEF(0x1818, 7, 2)      /* SQ_CAL_RESULT_EXT_LANE */
#define F_AT112G_SQ_INDV_EXT_EN  AT_SERDES_FLD_DEF(0x1810, 0, 0)      /* SQ_CAL_INDV_EXT_EN_LANE */
#define F_AT112G_SQ_OUT_LPF_RD   AT_SERDES_FLD_DEF(0x3260, 14, 14)    /* PIN_RX_SQ_OUT_LPF_RD_LANE */
#define F_AT112G_TSEN_ADC_DATA   AT_SERDES_FLD_DEF(0xA32C, 15, 0)
#define F_AT112G_ADD_ERR_EN      AT_SERDES_FLD_DEF(0x3024, 29, 29)
#define F_AT112G_ADD_ERR_NUM     AT_SERDES_FLD_DEF(0x3024, 28, 26)
#define F_AT112G_RX_CNT_RST      AT_SERDES_FLD_DEF(0x3264, 21, 21)    /* PT_RX_CNT_RST_LANE */
#define F_AT112G_CLI_CMD         AT_SERDES_FLD_DEF(0x6064, 7, 0)
#define F_AT112G_CLI_ARGS        AT_SERDES_FLD_DEF(0x6064, 31, 16)
#define F_AT112G_CLI_START       AT_SERDES_FLD_DEF(0x6064, 8, 8)
#define F_AT112G_RX_DP_TOP_EN    AT_SERDES_FLD_DEF(0x4808, 4, 4)      /* RX_DP_LMS_TOP_EN_LANE */
#define F_AT112G_RX_DTL_TOP_EN   AT_SERDES_FLD_DEF(0x4A30, 4, 4)      /* RX_DTL_LMS_TOP_EN_LANE */
#define F_AT112G_EQ_MON_CLK_EN   AT_SERDES_FLD_DEF(0x401C, 7, 7)      /* RX_EQ_MON_CLK_EN_LANE */
#define F_AT112G_MSE_START       AT_SERDES_FLD_DEF(0x45A0, 29, 29)
#define F_AT112G_MSE_DONE        AT_SERDES_FLD_DEF(0x45B0, 8, 8)
#define F_AT112G_MSE_EN          AT_SERDES_FLD_DEF(0x45A0, 31, 31)
#define F_AT112G_MSE_ADAPT_EN    AT_SERDES_FLD_DEF(0x45A0, 14, 14)    /* MSE_ANI_ADAPT_EN_LANE */
#define F_AT112G_MSE_MODE        AT_SERDES_FLD_DEF(0x45A0, 21, 21)
#define F_AT112G_MSE_CONT_MODE   AT_SERDES_FLD_DEF(0x45A0, 28, 28)
#define F_AT112G_MSE_RD_REQ      AT_SERDES_FLD_DEF(0x45A0, 23, 23)
#define F_AT112G_MSE_RD_ACK      AT_SERDES_FLD_DEF(0x45B0, 9, 9)
#define F_AT112G_MSE_VAL         AT_SERDES_FLD_DEF(0x45AC, 31, 16)
#define F_AT112G_RX_PAM2_EN      AT_SERDES_FLD_DEF(0x3208, 0, 0)
#define F_AT112G_PHY_ISOLATE     AT_SERDES_FLD_DEF(0xA318, 23, 23)    /* PHY_ISOLATE_MODE */
#define F_AT112G_BG_RDY          AT_SERDES_FLD_DEF(0xA420, 24, 24)
#define F_AT112G_FW_READY        AT_SERDES_FLD_DEF(0xA428, 14, 14)
#define F_AT112G_MCU_INIT_DONE   AT_SERDES_FLD_DEF(0xA200, 7, 7)
#define F_AT112G_PLL_SEL_LANE    AT_SERDES_FLD_DEF(0x607c, 9, 8)      /* PLL_SEL_LANE */
#define F_AT112G_TXFFE_PRESET_EXT AT_SERDES_FLD_DEF(0x6048, 27, 25)      /* trx_train_txffe_preset_ext_lane */


typedef enum
{
    TX_TRAIN_PAM4_PRESET1 = 1,
    TX_TRAIN_PAM4_PRESET2 = 2,
    TX_TRAIN_PAM4_PRESET3 = 3,
    TX_TRAIN_PAM4_PRESET_BUTT,
}_sys_at_serdes_txtrain_pam4_preset_e;

/* SERDES Speeds */
typedef enum
{
    AT112G_SERDES_1P0625G       = 0,    /* 1.0625 Gbps */
    AT112G_SERDES_1P2288G       = 1,    /* 1.2288 Gbps */
    AT112G_SERDES_1P25G         = 2,    /* 1.25 Gbps */
    AT112G_SERDES_2P125G        = 3,    /* 2.125 Gbps */
    AT112G_SERDES_2P4576G       = 4,    /* 2.4576 Gbps */
    AT112G_SERDES_2P5G          = 5,    /* 2.5 Gbps */
    AT112G_SERDES_2P578125G     = 46,   /* 2.578125 Gbps */
    AT112G_SERDES_3P125G        = 6,    /* 3.125 Gbps */
    AT112G_SERDES_4P25G         = 7,    /* 4.25 Gbps */
    AT112G_SERDES_4P9152G       = 8,    /* 4.9152 Gbps */
    AT112G_SERDES_5G            = 9,    /* 5 Gbps */
    AT112G_SERDES_5P15625G      = 10,   /* 5.15625 Gbps */
    AT112G_SERDES_6P144G        = 11,   /* 6.144 Gbps */
    AT112G_SERDES_6P25G         = 12,   /* 6.25 Gbps */
    AT112G_SERDES_7P5G          = 13,   /* 7.5 Gbps */
    AT112G_SERDES_8P5G          = 14,   /* 8.5 Gbps */
    AT112G_SERDES_9P8304G       = 15,   /* 9.8304 Gbps */
    AT112G_SERDES_10P137G       = 16,   /* 10.137 Gbps */
    AT112G_SERDES_10P3125G      = 17,   /* 10.3125 Gbps */
    AT112G_SERDES_10P51875G     = 18,   /* 10.51875 Gbps */
    AT112G_SERDES_12P16512G     = 19,   /* 12.16512 Gbps */
    AT112G_SERDES_12P1875G      = 20,   /* 12.1875 Gbps */
    AT112G_SERDES_12P5G         = 21,   /* 12.5 Gbps */
    AT112G_SERDES_12P8906G      = 22,   /* 12.8906 Gbps */
    AT112G_SERDES_14P025G       = 23,   /* 14.025 Gbps */
    AT112G_SERDES_15G           = 47,   /* 15 Gbps */
    AT112G_SERDES_20P625G       = 24,   /* 20.625 Gbps */
    AT112G_SERDES_24P33024G     = 25,   /* 24.33024 Gbps */
    AT112G_SERDES_25P78125G     = 26,   /* 25.78125 Gbps */
    AT112G_SERDES_26P5625G      = 27,   /* 26.5625 Gbps */
    AT112G_SERDES_27P1875G      = 48,   /* 27.1875 Gbps */
    AT112G_SERDES_27P5G         = 28,   /* 27.5 Gbps */
    AT112G_SERDES_28P05G        = 29,   /* 28.05 Gbps */
    AT112G_SERDES_28P125G       = 30,   /* 28.125 Gbps */
    AT112G_SERDES_32P5G         = 31,   /* 32.5 Gbps */
    AT112G_SERDES_46P25G        = 32,   /* 46.25 Gbps */
    AT112G_SERDES_50G           = 33,   /* 50 Gbps */
    AT112G_SERDES_51P5625G      = 34,   /* 51.5625 Gbps */
    AT112G_SERDES_53P125G       = 35,   /* 53.125 Gbps */
    AT112G_SERDES_56G           = 36,   /* 56 Gbps */
    AT112G_SERDES_56P1G         = 37,   /* 56.1 Gbps */
    AT112G_SERDES_56P25G        = 38,   /* 56.25 Gbps */
    AT112G_SERDES_106GP25G      = 39,   /* 106.25 Gbps */
    AT112G_SERDES_112G          = 40,   /* 112 Gbps */
    AT112G_SERDES_112P5G        = 41,   /* 112.5 Gbps */
    AT112G_SERDES_11P40625G     = 59,   /* 11.40625 Gbps */
    AT112G_SERDES_10P9375G      = 58,   /* 10.9375 Gbps */
    AT112G_SERDES_12P96875G     = 60,   /* 12.96875 Gbps */
    AT112G_SERDES_27P34375G     = 61,   /* 27.34375 Gbps */
    AT112G_SERDES_27P78125G     = 62,   /* 27.78125 Gbps */
    AT112G_SERDES_42P5G         = 56,   /* 42.5 Gbps */
    AT112G_SERDES_MAX_G         = 255   /* invalid */
} _sys_at_serdes_112g_speed_e;

/* Reference Frequency Clock */
typedef enum
{
    AT112G_REFFREQ_25MHZ        = 0,    /* 25 MHz */
    AT112G_REFFREQ_30MHZ        = 1,    /* 30 MHz */
    AT112G_REFFREQ_40MHZ        = 2,    /* 40 MHz */
    AT112G_REFFREQ_50MHZ        = 3,    /* 50 MHz */
    AT112G_REFFREQ_62P25MHZ     = 4,    /* 62.25 MHz */
    AT112G_REFFREQ_100MHZ       = 5,    /* 100 MHz */
    AT112G_REFFREQ_125MHZ       = 6,    /* 125 MHz */
    AT112G_REFFREQ156P25MHZ     = 7     /* 156.25 MHz */
} _sys_at_serdes_112g_reffreq_e;

/* TX and RX Data Bus Width */
typedef enum
{
    AT112G_DATABUS_32BIT        = 0,
    AT112G_DATABUS_40BIT        = 1,
    AT112G_DATABUS_64BIT        = 2,
    AT112G_DATABUS_80BIT        = 3,
    AT112G_DATABUS_128BIT       = 4,
    AT112G_DATABUS_160BIT       = 5,
    AT112G_DATABUSUNSUPPORT     = 6
} _sys_at_serdes_112g_data_width_e;

/* Data Path */
typedef enum
{
    AT112G_PATH_LOCAL_LB        = 0,    /* Local Analog Loopback */
    AT112G_PATH_EXTERNAL        = 1,
    AT112G_PATH_FAR_END_LB      = 2,
    AT112G_PATH_UNKNOWN         = 3
} _sys_at_serdes_112g_path_e;

/* Training Type */
typedef enum
{
    AT_SERDES_TRAINING_TRX        = 0,
    AT_SERDES_TRAINING_RX         = 1
} _sys_at_serdes_training_e;

/* Hardware Pins */
typedef enum
{
    AT112G_PIN_RESET            = 0,
    AT112G_PIN_ISOLATION        = 1,
    AT112G_PIN_BG_RDY           = 2,
    AT112G_PIN_SIF_SEL          = 3,
    AT112G_PIN_MCU_CLK          = 4,
    AT112G_PIN_DIRECTACCESS     = 5,    /* PIN_DIRECT_ACCESS_EN */
    AT112G_PIN_PRAM_FORCE       = 6,    /* PIN_PRAM_FORCE_RESET */
    AT112G_PIN_PRAM_RESET       = 7,
    AT112G_PIN_PRAM_SOC_EN      = 8,
    AT112G_PIN_PRAM_SIF_SEL     = 9,
    AT112G_PIN_PHY_MODE         = 10,
    AT112G_PIN_REFCLK_TX0       = 11,   /* PIN_REFCLK_SEL_TX0 */
    AT112G_PIN_REFCLK_TX1       = 12,   /* PIN_REFCLK_SEL_TX1 */
    AT112G_PIN_REFCLK_TX2       = 13,   /* PIN_REFCLK_SEL_TX2 */
    AT112G_PIN_REFCLK_TX3       = 14,   /* PIN_REFCLK_SEL_TX3 */
    AT112G_PIN_REFCLK_RX0       = 15,   /* PIN_REFCLK_SEL_RX0 */
    AT112G_PIN_REFCLK_RX1       = 16,   /* PIN_REFCLK_SEL_RX1 */
    AT112G_PIN_REFCLK_RX2       = 17,   /* PIN_REFCLK_SEL_RX2 */
    AT112G_PIN_REFCLK_RX3       = 18,   /* PIN_REFCLK_SEL_RX3 */
    AT112G_PIN_REF_FREF_TX0     = 19,   /* PIN_REF_FREF_TX0 */
    AT112G_PIN_REF_FREF_TX1     = 20,   /* PIN_REF_FREF_TX1 */
    AT112G_PIN_REF_FREF_TX2     = 21,   /* PIN_REF_FREF_TX2 */
    AT112G_PIN_REF_FREF_TX3     = 22,   /* PIN_REF_FREF_TX3 */
    AT112G_PIN_REF_FREF_RX0     = 23,   /* PIN_REF_FREF_RX0 */
    AT112G_PIN_REF_FREF_RX1     = 24,   /* PIN_REF_FREF_RX1 */
    AT112G_PIN_REF_FREF_RX2     = 25,   /* PIN_REF_FREF_RX2 */
    AT112G_PIN_REF_FREF_RX3     = 26,   /* PIN_REF_FREF_RX3 */
    AT112G_PIN_PHY_GEN_TX0      = 27,
    AT112G_PIN_PHY_GEN_TX1      = 28,
    AT112G_PIN_PHY_GEN_TX2      = 29,
    AT112G_PIN_PHY_GEN_TX3      = 30,
    AT112G_PIN_PHY_GEN_RX0      = 31,
    AT112G_PIN_PHY_GEN_RX1      = 32,
    AT112G_PIN_PHY_GEN_RX2      = 33,
    AT112G_PIN_PHY_GEN_RX3      = 34,
    AT112G_PIN_PU_PLL0          = 35,
    AT112G_PIN_PU_PLL1          = 36,
    AT112G_PIN_PU_PLL2          = 37,
    AT112G_PIN_PU_PLL3          = 38,
    AT112G_PIN_PU_RX0           = 39,
    AT112G_PIN_PU_RX1           = 40,
    AT112G_PIN_PU_RX2           = 41,
    AT112G_PIN_PU_RX3           = 42,
    AT112G_PIN_PU_TX0           = 43,
    AT112G_PIN_PU_TX1           = 44,
    AT112G_PIN_PU_TX2           = 45,
    AT112G_PIN_PU_TX3           = 46,
    AT112G_PIN_TX_IDLE0         = 47,
    AT112G_PIN_TX_IDLE1         = 48,
    AT112G_PIN_TX_IDLE2         = 49,
    AT112G_PIN_TX_IDLE3         = 50,
    AT112G_PIN_PU_IVREF         = 51,
    AT112G_PIN_RX_TRAIN_EN0     = 52,   /* PIN_RX_TRAIN_ENABLE0 */
    AT112G_PIN_RX_TRAIN_EN1     = 53,   /* PIN_RX_TRAIN_ENABLE1 */
    AT112G_PIN_RX_TRAIN_EN2     = 54,   /* PIN_RX_TRAIN_ENABLE2 */
    AT112G_PIN_RX_TRAIN_EN3     = 55,   /* PIN_RX_TRAIN_ENABLE3 */
    AT112G_PIN_RX_TRAIN_CO0     = 56,   /* PIN_RX_TRAIN_COMPLETE0 */
    AT112G_PIN_RX_TRAIN_CO1     = 57,   /* PIN_RX_TRAIN_COMPLETE1 */
    AT112G_PIN_RX_TRAIN_CO2     = 58,   /* PIN_RX_TRAIN_COMPLETE2 */
    AT112G_PIN_RX_TRAIN_CO3     = 59,   /* PIN_RX_TRAIN_COMPLETE3 */
    AT112G_PIN_RX_TRAIN_FA0     = 60,   /* PIN_RX_TRAIN_FAILED0 */
    AT112G_PIN_RX_TRAIN_FA1     = 61,   /* PIN_RX_TRAIN_FAILED1 */
    AT112G_PIN_RX_TRAIN_FA2     = 62,   /* PIN_RX_TRAIN_FAILED2 */
    AT112G_PIN_RX_TRAIN_FA3     = 63,   /* PIN_RX_TRAIN_FAILED3 */
    AT112G_PIN_TX_TRAIN_EN0     = 64,   /* PIN_TX_TRAIN_ENABLE0 */
    AT112G_PIN_TX_TRAIN_EN1     = 65,   /* PIN_TX_TRAIN_ENABLE1 */
    AT112G_PIN_TX_TRAIN_EN2     = 66,   /* PIN_TX_TRAIN_ENABLE2 */
    AT112G_PIN_TX_TRAIN_EN3     = 67,   /* PIN_TX_TRAIN_ENABLE3 */
    AT112G_PIN_TX_TRAIN_CO0     = 68,   /* PIN_TX_TRAIN_COMPLETE0 */
    AT112G_PIN_TX_TRAIN_CO1     = 69,   /* PIN_TX_TRAIN_COMPLETE1 */
    AT112G_PIN_TX_TRAIN_CO2     = 70,   /* PIN_TX_TRAIN_COMPLETE2 */
    AT112G_PIN_TX_TRAIN_CO3     = 71,   /* PIN_TX_TRAIN_COMPLETE3 */
    AT112G_PIN_TX_TRAIN_FA0     = 72,   /* PIN_TX_TRAIN_FAILED0 */
    AT112G_PIN_TX_TRAIN_FA1     = 73,   /* PIN_TX_TRAIN_FAILED1 */
    AT112G_PIN_TX_TRAIN_FA2     = 74,   /* PIN_TX_TRAIN_FAILED2 */
    AT112G_PIN_TX_TRAIN_FA3     = 75,   /* PIN_TX_TRAIN_FAILED3 */
    AT112G_PIN_SQ_DET_LPF0      = 76,   /* PIN_SQ_DETECTED_LPF0 */
    AT112G_PIN_SQ_DET_LPF1      = 77,   /* PIN_SQ_DETECTED_LPF1 */
    AT112G_PIN_SQ_DET_LPF2      = 78,   /* PIN_SQ_DETECTED_LPF2 */
    AT112G_PIN_SQ_DET_LPF3      = 79,   /* PIN_SQ_DETECTED_LPF3 */
    AT112G_PIN_RX_INIT0         = 80,
    AT112G_PIN_RX_INIT1         = 81,
    AT112G_PIN_RX_INIT2         = 82,
    AT112G_PIN_RX_INIT3         = 83,
    AT112G_PIN_RX_INITDONE0     = 84,   /* PIN_RX_INIT_DONE0 */
    AT112G_PIN_RX_INITDONE1     = 85,   /* PIN_RX_INIT_DONE1 */
    AT112G_PIN_RX_INITDONE2     = 86,   /* PIN_RX_INIT_DONE2 */
    AT112G_PIN_RX_INITDONE3     = 87,   /* PIN_RX_INIT_DONE3 */
    AT112G_PIN_AVDD_SEL         = 88,
    AT112G_PIN_SPD_CFG          = 89,
    AT112G_PIN_TX_RST0          = 90,   /*HssCmnCfg, cfgHssTxRstLane0*/
    AT112G_PIN_TX_RST1          = 91,   /*HssCmnCfg, cfgHssTxRstLane1*/
    AT112G_PIN_TX_RST2          = 92,   /*HssCmnCfg, cfgHssTxRstLane2*/
    AT112G_PIN_TX_RST3          = 93,   /*HssCmnCfg, cfgHssTxRstLane3*/
    AT112G_PIN_RX_RST0          = 94,   /*HssCmnCfg, cfgHssRxRstLane0*/
    AT112G_PIN_RX_RST1          = 95,   /*HssCmnCfg, cfgHssRxRstLane1*/
    AT112G_PIN_RX_RST2          = 96,   /*HssCmnCfg, cfgHssRxRstLane2*/
    AT112G_PIN_RX_RST3          = 97,   /*HssCmnCfg, cfgHssRxRstLane3*/
    AT112G_PIN_FW_READY         = 98,   /*HssCmnCfg, cfgHssFwReady*/
    AT112G_PIN_PLL_RDY_RX0      = 99,   /*HssMon, monHssPllReadyRxLane0*/
    AT112G_PIN_PLL_RDY_RX1      = 100,   /*HssMon, monHssPllReadyRxLane1*/
    AT112G_PIN_PLL_RDY_RX2      = 101,   /*HssMon, monHssPllReadyRxLane2*/
    AT112G_PIN_PLL_RDY_RX3      = 102,   /*HssMon, monHssPllReadyRxLane3*/
    AT112G_PIN_PLL_RDY_TX0      = 103,   /*HssMon, monHssPllReadyTxLane0*/
    AT112G_PIN_PLL_RDY_TX1      = 104,   /*HssMon, monHssPllReadyTxLane1*/
    AT112G_PIN_PLL_RDY_TX2      = 105,   /*HssMon, monHssPllReadyTxLane2*/
    AT112G_PIN_PLL_RDY_TX3      = 106,   /*HssMon, monHssPllReadyTxLane3*/
    AT112G_PIN_TX_RST_ACK0      = 107,   /*HssMon, monHssTxRstAckLane0*/
    AT112G_PIN_TX_RST_ACK1      = 108,   /*HssMon, monHssTxRstAckLane1*/
    AT112G_PIN_TX_RST_ACK2      = 109,   /*HssMon, monHssTxRstAckLane2*/
    AT112G_PIN_TX_RST_ACK3      = 110,   /*HssMon, monHssTxRstAckLane3*/
    AT112G_PIN_RX_RST_ACK0      = 111,   /*HssMon, monHssRxRstAckLane0*/
    AT112G_PIN_RX_RST_ACK1      = 112,   /*HssMon, monHssRxRstAckLane1*/
    AT112G_PIN_RX_RST_ACK2      = 113,   /*HssMon, monHssRxRstAckLane2*/
    AT112G_PIN_RX_RST_ACK3      = 114,   /*HssMon, monHssRxRstAckLane3*/
    AT112G_PIN_RX_GRAYCODE_EN0  = 115,   /*HssRxCfg, cfgHssRxGrayCodeEnLane0*/
    AT112G_PIN_RX_GRAYCODE_EN1  = 116,   /*HssRxCfg, cfgHssRxGrayCodeEnLane1*/
    AT112G_PIN_RX_GRAYCODE_EN2  = 117,   /*HssRxCfg, cfgHssRxGrayCodeEnLane2*/
    AT112G_PIN_RX_GRAYCODE_EN3  = 118,   /*HssRxCfg, cfgHssRxGrayCodeEnLane3*/
    AT112G_PIN_TX_GRAYCODE_EN0  = 119,   /*HssTxCfg, cfgHssTxGrayCodeEnLane0*/
    AT112G_PIN_TX_GRAYCODE_EN1  = 120,   /*HssTxCfg, cfgHssTxGrayCodeEnLane1*/
    AT112G_PIN_TX_GRAYCODE_EN2  = 121,   /*HssTxCfg, cfgHssTxGrayCodeEnLane2*/
    AT112G_PIN_TX_GRAYCODE_EN3  = 122,   /*HssTxCfg, cfgHssTxGrayCodeEnLane3*/
    AT112G_PIN_RX_PRECODE_EN0   = 123,   /*HssRxCfg, cfgHssRxPreCodeEnLane0*/
    AT112G_PIN_RX_PRECODE_EN1   = 124,   /*HssRxCfg, cfgHssRxPreCodeEnLane1*/
    AT112G_PIN_RX_PRECODE_EN2   = 125,   /*HssRxCfg, cfgHssRxPreCodeEnLane2*/
    AT112G_PIN_RX_PRECODE_EN3   = 126,   /*HssRxCfg, cfgHssRxPreCodeEnLane3*/
    AT112G_PIN_TX_PRECODE_EN0   = 127,   /*HssTxCfg, cfgHssTxPreCodeEnLane0*/
    AT112G_PIN_TX_PRECODE_EN1   = 128,   /*HssTxCfg, cfgHssTxPreCodeEnLane1*/
    AT112G_PIN_TX_PRECODE_EN2   = 129,   /*HssTxCfg, cfgHssTxPreCodeEnLane2*/
    AT112G_PIN_TX_PRECODE_EN3   = 130,   /*HssTxCfg, cfgHssTxPreCodeEnLane3*/
    AT112G_PIN_FORCE_PMA_RDY_EN0 = 131,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    AT112G_PIN_FORCE_PMA_RDY_EN1 = 132,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    AT112G_PIN_FORCE_PMA_RDY_EN2 = 133,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    AT112G_PIN_FORCE_PMA_RDY_EN3 = 134,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    AT112G_PIN_FORCE_PMA_RDY_VAL0 = 135,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane0*/
    AT112G_PIN_FORCE_PMA_RDY_VAL1 = 136,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane1*/
    AT112G_PIN_FORCE_PMA_RDY_VAL2 = 137,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane2*/
    AT112G_PIN_FORCE_PMA_RDY_VAL3 = 138,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane3*/
    AT112G_PIN_PRAM_CHECKSUM_RESET = 139,   /*HssPramCfg, cfgPramChecksumReset*/
    AT112G_PIN_PRAM_CHECKSUM       = 140,   /*HssPramMon, monPramChecksum*/
    AT112G_PIN_PRAM_CHECKSUM_EN    = 141,   /*HssPramCfg, cfgPramChecksumEn*/
    AT112G_PIN_PRAM_CHECKSUM_SEL   = 142,   /*HssPramCfg, cfgPramChecksumSel*/
    AT112G_PIN_MCU_INIT_DONE       = 143,   /*HssMcuMon, monHssMcuInitDone*/
    AT112G_PIN_RX_DTL_CLAMP0    = 144,
    AT112G_PIN_RX_DTL_CLAMP1    = 145,
    AT112G_PIN_RX_DTL_CLAMP2    = 146,
    AT112G_PIN_RX_DTL_CLAMP3    = 147,
} _sys_at_serdes_112g_pin_e;

/* AVDD Select */
typedef enum
{
    AT112G_AVDD_0P95V           = 0x2,
    AT112G_AVDD_1P0V            = 0x3,
    AT112G_AVDD_1P05V           = 0x4,
    AT112G_AVDD_1P1V            = 0x5,
    AT112G_AVDD_1P15V           = 0x6,
    AT112G_AVDD_1P2V            = 0x7,
} _sys_at_serdes_112g_avdd_e;

/* Speed Configuration */
typedef enum
{
    AT112G_SPD_CFG_4_PLL      = 2,
    AT112G_SPD_CFG_PLL_TS     = 3,
} _sys_at_serdes_112g_spd_cfg_e;

/* Reference Clock selection Group */
typedef enum
{
    AT112G_REFCLK_SELGROUP1     = 0,
    AT112G_REFCLK_SELGROUP2     = 1
} _sys_at_serdes_112g_refclk_e;

/*112G macro define end*/


/*56G macro define start*/

#define F_AT56G_LANE_SEL          AT_SERDES_FLD_DEF(0xA318, 31, 28)
#define F_AT56G_DFE_EN            AT_SERDES_FLD_DEF(0x5648, 29, 29)
#define F_AT56G_RSRVD_INPUT_RX_RD AT_SERDES_FLD_DEF(0x5604, 15, 0)     /* PIN_RESERVED_INPUT_RX_RD_LANE */
#define F_AT56G_RSRVD_INPUT_RX    AT_SERDES_FLD_DEF(0x562C, 31, 16)    /* RESERVED_INPUT_RX_LANE */
#define F_AT56G_RSRVD_INPUT_RX_FM AT_SERDES_FLD_DEF(0x562C, 15, 15)    /* RESERVED_INPUT_RX_FM_REG_LANE */
#define F_AT56G_BROADCAST         AT_SERDES_FLD_DEF(0xA318, 27, 27)
#define F_AT56G_PLL_RS_LOCK       AT_SERDES_FLD_DEF(0x5800, 30, 30)
#define F_AT56G_PLL_TS_LOCK       AT_SERDES_FLD_DEF(0x5700, 6, 6)
#define F_AT56G_PH_OS_DAT         AT_SERDES_FLD_DEF(0x6DDC, 7, 0)
#define F_AT56G_ALIGN90_CAL_7_0   AT_SERDES_FLD_DEF(0x19B8, 7, 0)      /* RX_ALIGN90_CAL_SETTING_LANE[7:0] */
#define F_AT56G_SQ_RES_RD         AT_SERDES_FLD_DEF(0x1AF0, 6, 1)
#define F_AT56G_SQ_RES_EXT        AT_SERDES_FLD_DEF(0x1AEC, 7, 2)
#define F_AT56G_SQ_INDV           AT_SERDES_FLD_DEF(0x1AE4, 0, 0)
#define F_AT56G_TX_SEL_BITS       AT_SERDES_FLD_DEF(0x3034, 31, 31)
#define F_AT56G_RX_SEL_BITS       AT_SERDES_FLD_DEF(0x3204, 31, 31)
#define F_AT56G_TX_PAM2_EN        AT_SERDES_FLD_DEF(0x303C, 30, 30)
#define F_AT56G_RX_PAM2_EN        AT_SERDES_FLD_DEF(0x3204, 0, 0)
#define F_AT56G_RX_ANA_PAM2_EN    AT_SERDES_FLD_DEF(0x3204, 28, 28)
#define F_AT56G_RX_EQ_PAM2_EN     AT_SERDES_FLD_DEF(0x3204, 29, 29)
#define F_AT56G_TXD_INV           AT_SERDES_FLD_DEF(0x3024, 30, 30)
#define F_AT56G_RXD_INV           AT_SERDES_FLD_DEF(0x3248, 29, 29)
#define F_AT56G_FW_MAJOR_VER      AT_SERDES_FLD_DEF(0xE600, 31, 24)
#define F_AT56G_FW_MINOR_VER      AT_SERDES_FLD_DEF(0xE600, 23, 16)
#define F_AT56G_FW_PATCH_VER      AT_SERDES_FLD_DEF(0xE600, 15, 8)
#define F_AT56G_FW_BUILD_VER      AT_SERDES_FLD_DEF(0xE600, 7, 0)
#define F_AT56G_TX_C0             AT_SERDES_FLD_DEF(0x30CC, 29, 24)
#define F_AT56G_TX_C1             AT_SERDES_FLD_DEF(0x30CC, 22, 17)
#define F_AT56G_TX_C2             AT_SERDES_FLD_DEF(0x30CC, 14, 9)
#define F_AT56G_TX_C3             AT_SERDES_FLD_DEF(0x30CC, 6, 1)
#define F_AT56G_TX_C4             AT_SERDES_FLD_DEF(0x30D0, 30, 25)
#define F_AT56G_TX_C5             AT_SERDES_FLD_DEF(0x30D0, 22, 17)
#define F_AT56G_TX_C0_FORCE       AT_SERDES_FLD_DEF(0x30CC, 30, 30)
#define F_AT56G_TX_C1_FORCE       AT_SERDES_FLD_DEF(0x30CC, 23, 23)
#define F_AT56G_TX_C2_FORCE       AT_SERDES_FLD_DEF(0x30CC, 15, 15)
#define F_AT56G_TX_C3_FORCE       AT_SERDES_FLD_DEF(0x30CC, 7, 7)
#define F_AT56G_TX_C4_FORCE       AT_SERDES_FLD_DEF(0x30D0, 31, 31)
#define F_AT56G_TX_C5_FORCE       AT_SERDES_FLD_DEF(0x30D0, 23, 23)
#define F_AT56G_TX_UP             AT_SERDES_FLD_DEF(0x30D0, 8, 8)
#define F_AT56G_TX_UP_FORCE       AT_SERDES_FLD_DEF(0x30D0, 7, 7)
#define F_AT56G_ANA_TX_C0         AT_SERDES_FLD_DEF(0x30D4, 29, 24)
#define F_AT56G_ANA_TX_C1         AT_SERDES_FLD_DEF(0x30D4, 21, 16)
#define F_AT56G_ANA_TX_C2         AT_SERDES_FLD_DEF(0x30D4, 13, 8)
#define F_AT56G_ANA_TX_C3         AT_SERDES_FLD_DEF(0x30D4, 5, 0)
#define F_AT56G_ANA_TX_C4         AT_SERDES_FLD_DEF(0x30D8, 29, 24)
#define F_AT56G_ANA_TX_C5         AT_SERDES_FLD_DEF(0x30D8, 21, 16)
#define F_AT56G_TX_FIR_TAP_POL    AT_SERDES_FLD_DEF(0x30D0, 6, 1)
#define F_AT56G_TX_FIR_TAP_POL_F  AT_SERDES_FLD_DEF(0x30D0, 0, 0)      /* TX_FIR_TAP_POL_FORCE_LANE */
#define F_AT56G_TO_ANA_TX_FIR_POL AT_SERDES_FLD_DEF(0x30D8, 13, 8)     /* TO_ANA_TX_FIR_TAP_POL_LANE */
#define F_AT56G_ADD_ERR_EN        AT_SERDES_FLD_DEF(0x3024, 29, 29)
#define F_AT56G_ADD_ERR_NUM       AT_SERDES_FLD_DEF(0x3024, 28, 26)
#define F_AT56G_CURRENT1_SEL      AT_SERDES_FLD_DEF(0x1050, 3, 0)
#define F_AT56G_RL1_SEL           AT_SERDES_FLD_DEF(0x1060, 3, 0)
#define F_AT56G_RL1_EXTRA         AT_SERDES_FLD_DEF(0x1038, 2, 0)
#define F_AT56G_RES1_SEL          AT_SERDES_FLD_DEF(0x1058, 3, 0)
#define F_AT56G_CAP1_SEL_G        AT_SERDES_FLD_DEF(0x1048, 3, 0)
#define F_AT56G_EN_MID_FREQ       AT_SERDES_FLD_DEF(0x1088, 4, 4)
#define F_AT56G_CS1_MID           AT_SERDES_FLD_DEF(0x1040, 5, 4)
#define F_AT56G_RS1_MID           AT_SERDES_FLD_DEF(0x1040, 7, 6)
#define F_AT56G_CURRENT2_SEL      AT_SERDES_FLD_DEF(0x1054, 3, 0)
#define F_AT56G_RL2_SEL           AT_SERDES_FLD_DEF(0x1064, 3, 0)
#define F_AT56G_RL2_TUNE_G        AT_SERDES_FLD_DEF(0x0100, 2, 0)
#define F_AT56G_RES2_SEL          AT_SERDES_FLD_DEF(0x105C, 3, 0)
#define F_AT56G_CAP2_SEL          AT_SERDES_FLD_DEF(0x104C, 3, 0)
#define F_AT56G_CTLE_CL1_SEL      AT_SERDES_FLD_DEF(0x103C, 1, 0)
#define F_AT56G_CTLE_CL2_SEL      AT_SERDES_FLD_DEF(0x103C, 3, 2)
#define F_AT56G_RX_SELMUFI        AT_SERDES_FLD_DEF(0x3200, 3, 0)
#define F_AT56G_RX_SELMUFF        AT_SERDES_FLD_DEF(0x3200, 7, 4)
#define F_AT56G_REG_SELMUPI       AT_SERDES_FLD_DEF(0x10CC, 2, 0)
#define F_AT56G_REG_SELMUPF       AT_SERDES_FLD_DEF(0x10C4, 2, 0)
#define F_AT56G_DC_D_T_E_SM       AT_SERDES_FLD_DEF(0x4108, 22, 16)
#define F_AT56G_DC_E_E_SM         AT_SERDES_FLD_DEF(0x410C, 22, 16)
#define F_AT56G_VREF_T_E_SM       AT_SERDES_FLD_DEF(0x4110, 14, 8)
#define F_AT56G_F0_D_T_E_SM       AT_SERDES_FLD_DEF(0x4114, 5, 0)
#define F_AT56G_F1_D_T_E_SM       AT_SERDES_FLD_DEF(0x4118, 22, 16)
#define F_AT56G_F1P5_E_SM         AT_SERDES_FLD_DEF(0x4140, 13, 8)
#define F_AT56G_F2_D_T_E_SM       AT_SERDES_FLD_DEF(0x4120, 5, 0)
#define F_AT56G_F3_T_E_SM         AT_SERDES_FLD_DEF(0x4124, 22, 16)
#define F_AT56G_F4_T_E_SM         AT_SERDES_FLD_DEF(0x4128, 14, 8)
#define F_AT56G_F5_LSB_E_SM       AT_SERDES_FLD_DEF(0x4128, 21, 16)
#define F_AT56G_F5_MSB_E_SM       AT_SERDES_FLD_DEF(0x4128, 29, 24)
#define F_AT56G_F6_LSB_E_SM       AT_SERDES_FLD_DEF(0x412C, 5, 0)
#define F_AT56G_F6_MSB_E_SM       AT_SERDES_FLD_DEF(0x412C, 13, 8)
#define F_AT56G_F7_LSB_E_SM       AT_SERDES_FLD_DEF(0x412C, 21, 16)
#define F_AT56G_F7_MSB_E_SM       AT_SERDES_FLD_DEF(0x412C, 29, 24)
#define F_AT56G_F8_LSB_E_SM       AT_SERDES_FLD_DEF(0x4130, 13, 8)
#define F_AT56G_F8_MSB_E_SM       AT_SERDES_FLD_DEF(0x4130, 21, 16)
#define F_AT56G_F9_LSB_E_SM       AT_SERDES_FLD_DEF(0x4134, 5, 0)
#define F_AT56G_F9_MSB_E_SM       AT_SERDES_FLD_DEF(0x4134, 13, 8)
#define F_AT56G_F10_LSB_E_SM      AT_SERDES_FLD_DEF(0x4134, 29, 24)
#define F_AT56G_F10_MSB_E_SM      AT_SERDES_FLD_DEF(0x4138, 5, 0)
#define F_AT56G_F11_E_SM          AT_SERDES_FLD_DEF(0x4138, 20, 16)
#define F_AT56G_F12_E_SM          AT_SERDES_FLD_DEF(0x413C, 4, 0)
#define F_AT56G_F13_E_SM          AT_SERDES_FLD_DEF(0x413C, 20, 16)
#define F_AT56G_F14_E_SM          AT_SERDES_FLD_DEF(0x413C, 28, 24)
#define F_AT56G_F15_E_SM          AT_SERDES_FLD_DEF(0x4140, 4, 0)
#define F_AT56G_FF0_E_SM          AT_SERDES_FLD_DEF(0x4130, 5, 0)
#define F_AT56G_FF1_E_SM          AT_SERDES_FLD_DEF(0x4130, 29, 24)
#define F_AT56G_FF2_E_SM          AT_SERDES_FLD_DEF(0x4134, 21, 16)
#define F_AT56G_FF3_E_SM          AT_SERDES_FLD_DEF(0x4138, 13, 8)
#define F_AT56G_FF4_E_SM          AT_SERDES_FLD_DEF(0x4138, 29, 24)
#define F_AT56G_FF5_E_SM          AT_SERDES_FLD_DEF(0x413C, 13, 8)
#define F_AT56G_DC_D_M_E_SM       AT_SERDES_FLD_DEF(0x4108, 14, 8)
#define F_AT56G_VREF_M_E_SM       AT_SERDES_FLD_DEF(0x4110, 6, 0)
#define F_AT56G_F0_D_M_E_SM       AT_SERDES_FLD_DEF(0x4110, 29, 24)
#define F_AT56G_F1_D_M_E_SM       AT_SERDES_FLD_DEF(0x4118, 14, 8)
#define F_AT56G_F2_D_M_E_SM       AT_SERDES_FLD_DEF(0x411C, 29, 24)
#define F_AT56G_F3_M_E_SM         AT_SERDES_FLD_DEF(0x4124, 14, 8)
#define F_AT56G_F4_M_E_SM         AT_SERDES_FLD_DEF(0x4128, 6, 0)
#define F_AT56G_DC_D_B_E_SM       AT_SERDES_FLD_DEF(0x4108, 6, 0)
#define F_AT56G_VREF_B_E_SM       AT_SERDES_FLD_DEF(0x410C, 30, 24)
#define F_AT56G_F0_D_B_E_SM       AT_SERDES_FLD_DEF(0x4110, 21, 16)
#define F_AT56G_F1_D_B_E_SM       AT_SERDES_FLD_DEF(0x4118, 6, 0)
#define F_AT56G_F2_D_B_E_SM       AT_SERDES_FLD_DEF(0x411C, 21, 16)
#define F_AT56G_F3_B_E_SM         AT_SERDES_FLD_DEF(0x4124, 6, 0)
#define F_AT56G_F4_B_E_SM         AT_SERDES_FLD_DEF(0x4124, 30, 24)
#define F_AT56G_F0_DC_SHIFT       AT_SERDES_FLD_DEF(0x1088, 6, 5)
#define F_AT56G_DFE_RES_F0        AT_SERDES_FLD_DEF(0x106C, 5, 4)
#define F_AT56G_DFE_F0_RES_DOUBLE AT_SERDES_FLD_DEF(0x1068, 3, 3)
#define F_AT56G_F0_D_T_O_2C       AT_SERDES_FLD_DEF(0x418C, 7, 0)
#define F_AT56G_F0_S_T_O_2C       AT_SERDES_FLD_DEF(0x418C, 31, 24)
#define F_AT56G_F0_D_T_E_2C       AT_SERDES_FLD_DEF(0x41C8, 7, 0)
#define F_AT56G_F0_S_T_E_2C       AT_SERDES_FLD_DEF(0x41C8, 31, 24)
#define F_AT56G_F0_D_M_O_2C       AT_SERDES_FLD_DEF(0x4188, 31, 24)
#define F_AT56G_F0_S_M_O_2C       AT_SERDES_FLD_DEF(0x418C, 23, 16)
#define F_AT56G_F0_D_M_E_2C       AT_SERDES_FLD_DEF(0x41C4, 31, 24)
#define F_AT56G_F0_S_M_E_2C       AT_SERDES_FLD_DEF(0x41C8, 23, 16)
#define F_AT56G_F0_D_B_O_2C       AT_SERDES_FLD_DEF(0x4188, 23, 16)
#define F_AT56G_F0_S_B_O_2C       AT_SERDES_FLD_DEF(0x418C, 15, 8)
#define F_AT56G_F0_D_B_E_2C       AT_SERDES_FLD_DEF(0x41C4, 23, 16)
#define F_AT56G_F0_S_B_E_2C       AT_SERDES_FLD_DEF(0x41C8, 15, 8)
#define F_AT56G_DFE_ADAPT         AT_SERDES_FLD_DEF(0x4000, 13, 13)
#define F_AT56G_CLI_CMD           AT_SERDES_FLD_DEF(0x6068, 7, 0)
#define F_AT56G_CLI_ARGS          AT_SERDES_FLD_DEF(0x606C, 31, 0)
#define F_AT56G_CLI_START         AT_SERDES_FLD_DEF(0x6068, 8, 8)
#define F_AT56G_DFE_F0X_SEL       AT_SERDES_FLD_DEF(0x401C, 14, 10)
#define F_AT56G_DFE_LOAD_EN       AT_SERDES_FLD_DEF(0x6DD0, 15, 15)
#define F_AT56G_TRX_TIMER         AT_SERDES_FLD_DEF(0x5018, 31, 16)
#define F_AT56G_RX_TIMER          AT_SERDES_FLD_DEF(0x5018, 15, 0)
#define F_AT56G_TX_TIMER_EN       AT_SERDES_FLD_DEF(0x6034, 29, 29)
#define F_AT56G_RX_TIMER_EN       AT_SERDES_FLD_DEF(0x6034, 30, 30)
#define F_AT56G_D_TX2RX_LPBK      AT_SERDES_FLD_DEF(0x3248, 31, 31)
#define F_AT56G_A_TX2RX_LPBK      AT_SERDES_FLD_DEF(0x1130, 3, 3)
#define F_AT56G_D_RX2TX_LPBK      AT_SERDES_FLD_DEF(0x3024, 31, 31)
#define F_AT56G_DTL_CLAMPING      AT_SERDES_FLD_DEF(0x3260, 26, 24)    /* DTL_CLAMPING_SEL */
#define F_AT56G_R2T_NO_STOP       AT_SERDES_FLD_DEF(0x3024, 25, 25)    /* RX2TX_FIFO_NO_STOP */
#define F_AT56G_R2T_RD_START      AT_SERDES_FLD_DEF(0x3024, 24, 24)    /* RX2TX_FIFO_RD_START_POINT */
#define F_AT56G_FOFFSET_DIS       AT_SERDES_FLD_DEF(0x3268, 16, 16)    /* RX_FOFFSET_DISABLE */
#define F_AT56G_PU_LB             AT_SERDES_FLD_DEF(0x10B8, 3, 3)
#define F_AT56G_DTL_SQ_DET_EN     AT_SERDES_FLD_DEF(0x3260, 13, 13)
#define F_AT56G_DFE_SQ_EN         AT_SERDES_FLD_DEF(0x4040, 29, 29)
#define F_AT56G_CLI_START         AT_SERDES_FLD_DEF(0x6068, 8, 8)
#define F_AT56G_TX_PAT_SEL        AT_SERDES_FLD_DEF(0x3098, 29, 24)
#define F_AT56G_RX_PAT_SEL        AT_SERDES_FLD_DEF(0x3280, 29, 24)
#define F_AT56G_TXD_SWAP          AT_SERDES_FLD_DEF(0x3024, 18, 18)
#define F_AT56G_TXDATA_SWAP       AT_SERDES_FLD_DEF(0x3024, 5, 5)
#define F_AT56G_RXD_SWAP          AT_SERDES_FLD_DEF(0x3248, 27, 27)
#define F_AT56G_RXDATA_SWAP       AT_SERDES_FLD_DEF(0x3248, 24, 24)
#define F_AT56G_RX_CNT_4732       AT_SERDES_FLD_DEF(0x3290, 31, 16)
#define F_AT56G_RX_CNT_3100       AT_SERDES_FLD_DEF(0x3294, 31, 0)
#define F_AT56G_RX_ERR_4732       AT_SERDES_FLD_DEF(0x3298, 31, 16)
#define F_AT56G_RX_ERR_3100       AT_SERDES_FLD_DEF(0x329C, 31, 0)
#define F_AT56G_TX_UP_7948        AT_SERDES_FLD_DEF(0x309C, 31, 0)
#define F_AT56G_TX_UP_4716        AT_SERDES_FLD_DEF(0x30A0, 31, 0)
#define F_AT56G_TX_UP_1500        AT_SERDES_FLD_DEF(0x30A4, 31, 16)
#define F_AT56G_RX_UP_7948        AT_SERDES_FLD_DEF(0x3284, 31, 0)
#define F_AT56G_RX_UP_4716        AT_SERDES_FLD_DEF(0x3288, 31, 0)
#define F_AT56G_RX_UP_1500        AT_SERDES_FLD_DEF(0x328C, 31, 16)
#define F_AT56G_TX_PHYREADY       AT_SERDES_FLD_DEF(0x3098, 30, 30)
#define F_AT56G_RX_PHYREADY       AT_SERDES_FLD_DEF(0x3280, 22, 22)
#define F_AT56G_TX_EN_MODE        AT_SERDES_FLD_DEF(0x3098, 3, 2)
#define F_AT56G_RX_EN_MODE        AT_SERDES_FLD_DEF(0x3280, 31, 30)
#define F_AT56G_TX_EN             AT_SERDES_FLD_DEF(0x3098, 31, 31)
#define F_AT56G_RX_EN             AT_SERDES_FLD_DEF(0x3280, 23, 23)
#define F_AT56G_TRX_EN            AT_SERDES_FLD_DEF(0x328C, 8, 8)
#define F_AT56G_TX_RST            AT_SERDES_FLD_DEF(0x3098, 5, 5)
#define F_AT56G_RX_RST            AT_SERDES_FLD_DEF(0x328C, 7, 7)
#define F_AT56G_RX_LOCK           AT_SERDES_FLD_DEF(0x328C, 0, 0)
#define F_AT56G_RX_PASS           AT_SERDES_FLD_DEF(0x328C, 1, 1)
#define F_AT56G_RX_CNT_RST        AT_SERDES_FLD_DEF(0x3280, 21, 21)
#define F_AT56G_DFE_RATE          AT_SERDES_FLD_DEF(0x4010, 9, 8)
#define F_AT56G_DFE_UP_DIS        AT_SERDES_FLD_DEF(0x5648, 25, 25)    /* DFE_UPDATE_DIS_LANE */
#define F_AT56G_TRAIN_DONE        AT_SERDES_FLD_DEF(0x608C, 0, 0)
#define F_AT56G_MCU_DEBUGF        AT_SERDES_FLD_DEF(0x34F4, 31, 24)
#define F_AT56G_DFE_SAT_EN        AT_SERDES_FLD_DEF(0x4040, 31, 30)
#define F_AT56G_TSEN_DATA         AT_SERDES_FLD_DEF(0xA32C, 15, 0)
#define F_AT56G_ESM_PATH_SEL      AT_SERDES_FLD_DEF(0x6058, 16, 16)
#define F_AT56G_ESM_DFEADAPT      AT_SERDES_FLD_DEF(0x6058, 13, 10)
#define F_AT56G_ADAPT_EVEN        AT_SERDES_FLD_DEF(0x6DE4, 8, 8)
#define F_AT56G_ADAPT_ODD         AT_SERDES_FLD_DEF(0x6DE4, 9, 9)
#define F_AT56G_ESM_EN            AT_SERDES_FLD_DEF(0x6058, 18, 18)
#define F_AT56G_EOM_READY         AT_SERDES_FLD_DEF(0x603C, 3, 3)
#define F_AT56G_ESM_LPNUM         AT_SERDES_FLD_DEF(0x6078, 15, 0)
#define F_AT56G_ESM_PHASE         AT_SERDES_FLD_DEF(0x6078, 26, 16)
#define F_AT56G_ESM_VOLTAGE       AT_SERDES_FLD_DEF(0x603C, 15, 8)
#define F_AT56G_EOM_DFE_CALL      AT_SERDES_FLD_DEF(0x603C, 4, 4)
#define F_AT56G_VC_T_P_3100       AT_SERDES_FLD_DEF(0x4220, 31, 0)     /* EOM_VLD_CNT_TOP_P [31:00] */
#define F_AT56G_VC_T_P_3932       AT_SERDES_FLD_DEF(0x4238, 23, 16)
#define F_AT56G_VC_T_N_3100       AT_SERDES_FLD_DEF(0x422C, 31, 0)
#define F_AT56G_VC_T_N_3932       AT_SERDES_FLD_DEF(0x423C, 23, 16)
#define F_AT56G_VC_M_P_3100       AT_SERDES_FLD_DEF(0x4224, 31, 0)
#define F_AT56G_VC_M_P_3932       AT_SERDES_FLD_DEF(0x4238, 15, 8)
#define F_AT56G_VC_M_N_3100       AT_SERDES_FLD_DEF(0x4230, 31, 0)
#define F_AT56G_VC_M_N_3932       AT_SERDES_FLD_DEF(0x423C, 15, 8)
#define F_AT56G_VC_B_P_3100       AT_SERDES_FLD_DEF(0x4228, 31, 0)
#define F_AT56G_VC_B_P_3932       AT_SERDES_FLD_DEF(0x4238, 7, 0)
#define F_AT56G_VC_B_N_3100       AT_SERDES_FLD_DEF(0x4234, 31, 0)
#define F_AT56G_VC_B_N_3932       AT_SERDES_FLD_DEF(0x423C, 7, 0)
#define F_AT56G_EOM_EC_T_P        AT_SERDES_FLD_DEF(0x4200, 31, 0)
#define F_AT56G_EOM_EC_T_N        AT_SERDES_FLD_DEF(0x420C, 31, 0)
#define F_AT56G_EOM_EC_M_P        AT_SERDES_FLD_DEF(0x4204, 31, 0)
#define F_AT56G_EOM_EC_M_N        AT_SERDES_FLD_DEF(0x4210, 31, 0)
#define F_AT56G_EOM_EC_B_P        AT_SERDES_FLD_DEF(0x4208, 31, 0)
#define F_AT56G_EOM_EC_B_N        AT_SERDES_FLD_DEF(0x4214, 31, 0)
#define F_AT56G_PHY_ISOLATE       AT_SERDES_FLD_DEF(0xA318, 23, 23)    /* PHY_ISOLATE_MODE */
#define F_AT56G_FW_READY          AT_SERDES_FLD_DEF(0xA424, 14, 14)
#define F_AT56G_MCU_INIT_DONE     AT_SERDES_FLD_DEF(0xA200, 7, 7)
#define F_AT56G_BG_RDY            AT_SERDES_FLD_DEF(0xA41C, 24, 24)
#define F_AT56G_RX_INIT           AT_SERDES_FLD_DEF(0x5630, 24, 24)
#define F_AT56G_RX_INIT_DONE      AT_SERDES_FLD_DEF(0x3200, 19, 19)
#define F_AT56G_PU_IVREF          AT_SERDES_FLD_DEF(0xA420, 2, 2)
#define F_AT56G_PU_IVREF_FM_REG   AT_SERDES_FLD_DEF(0xA420, 1, 1)
#define F_AT56G_PU_TX             AT_SERDES_FLD_DEF(0x5530, 13, 13)
#define F_AT56G_ANA_PU_TX         AT_SERDES_FLD_DEF(0x3000, 30, 30)
#define F_AT56G_ANA_PU_TX_FORCE   AT_SERDES_FLD_DEF(0x3000, 31, 31)
#define F_AT56G_PU_RX             AT_SERDES_FLD_DEF(0x5624, 8, 8)
#define F_AT56G_ANA_PU_RX         AT_SERDES_FLD_DEF(0x3200, 30, 30)
#define F_AT56G_ANA_PU_RX_FORCE   AT_SERDES_FLD_DEF(0x3200, 31, 31)
#define F_AT56G_PU_PLL            AT_SERDES_FLD_DEF(0x5530, 15, 15)
#define F_AT56G_TX_IDLE           AT_SERDES_FLD_DEF(0x3014, 18, 18)
#define F_AT56G_PHY_MODE          AT_SERDES_FLD_DEF(0xA420, 14, 12)
#define F_AT56G_REF_FREF_TX       AT_SERDES_FLD_DEF(0x5538, 23, 19)    /* REF_FREF_SEL_TX_LANE */
#define F_AT56G_REF_FREF_RX       AT_SERDES_FLD_DEF(0x5634, 30, 26)    /* REF_FREF_SEL_RX_LANE */
#define F_AT56G_REFCLK_SEL_TX     AT_SERDES_FLD_DEF(0x5538, 17, 17)
#define F_AT56G_REFCLK_SEL_RX     AT_SERDES_FLD_DEF(0x5634, 24, 24)
#define F_AT56G_PHY_GEN_TX        AT_SERDES_FLD_DEF(0x5530, 22, 17)
#define F_AT56G_PHY_GEN_RX        AT_SERDES_FLD_DEF(0x5624, 15, 10)
#define F_AT56G_MCU_FREQ          AT_SERDES_FLD_DEF(0xA41C, 15, 0)
#define F_AT56G_RX_TRAIN_ENA      AT_SERDES_FLD_DEF(0x5630, 22, 22)
#define F_AT56G_RX_TRAIN_COM      AT_SERDES_FLD_DEF(0x5020, 4, 4)
#define F_AT56G_RX_TRAIN_FAI      AT_SERDES_FLD_DEF(0x5020, 3, 3)
#define F_AT56G_TX_TRAIN_ENA      AT_SERDES_FLD_DEF(0x5630, 16, 16)
#define F_AT56G_TX_TRAIN_COM      AT_SERDES_FLD_DEF(0x5020, 6, 6)
#define F_AT56G_TX_TRAIN_FAI      AT_SERDES_FLD_DEF(0x5020, 5, 5)
#define F_AT56G_RX_SQ_OUT         AT_SERDES_FLD_DEF(0x3270, 14, 14)
#define F_AT56G_AVDD_SEL          AT_SERDES_FLD_DEF(0xA41C, 28, 26)
#define F_AT56G_SPD_CFG           AT_SERDES_FLD_DEF(0xA420, 7, 4)
#define F_AT56G_TX_GRAY_EN        AT_SERDES_FLD_DEF(0x3098, 6, 6)
#define F_AT56G_RX_GRAY_EN        AT_SERDES_FLD_DEF(0x3280, 15, 15)
#define F_AT56G_TXDATA_PRECODE_EN AT_SERDES_FLD_DEF(0x5538, 13, 13)    /* TXDATA_PRE_CODE_EN_LANE */
#define F_AT56G_RXDATA_PRECODE_EN AT_SERDES_FLD_DEF(0x5644, 28, 28)    /* RXDATA_PRE_CODE_EN_LANE */
#define F_AT56G_PLL_READY_TX      AT_SERDES_FLD_DEF(0x3000, 20, 20)
#define F_AT56G_PLL_READY_RX      AT_SERDES_FLD_DEF(0x3200, 24, 24)
#define F_AT56G_RESET_CORE_TX     AT_SERDES_FLD_DEF(0x5538, 28, 28)
#define F_AT56G_RESET_CORE_RX     AT_SERDES_FLD_DEF(0x5630, 0, 0)
#define F_AT56G_RESET_CORE_ACK_TX AT_SERDES_FLD_DEF(0x3000, 21, 21)    /* RESET_CORE_ACK_TX_LANE */
#define F_AT56G_RESET_CORE_ACK_RX AT_SERDES_FLD_DEF(0x321C, 2, 2)      /* RESET_CORE_ACK_RX_LANE */
#define F_AT56G_MCU_REMOTE_CMD    AT_SERDES_FLD_DEF(0x5638, 31, 0)     /* MCU_REMOTE_COMMAND_LANE */
#define F_AT56G_MCU_REMOTE_CMD_FM AT_SERDES_FLD_DEF(0x563C, 31, 31)    /* MCU_REMOTE_COMMAND_FM_REG_LANE */
#define F_AT56G_MCU_REMOTE_CMD_RD AT_SERDES_FLD_DEF(0x5618, 31, 0)     /* PIN_MCU_REMOTE_COMMAND_RD_LANE */
#define F_AT56G_MCU_REMOTE_STA    AT_SERDES_FLD_DEF(0x5640, 31, 0)
#define F_AT56G_MCU_REMOTE_STA_FM AT_SERDES_FLD_DEF(0x5644, 31, 31)    /* MCU_REMOTE_STATUS_FM_REG_LANE */
#define F_AT56G_MCU_REMOTE_STA_RD AT_SERDES_FLD_DEF(0x5620, 31, 0)     /* PIN_MCU_REMOTE_STATUS_RD_LANE */
#define F_AT56G_MCU_REMOTE_REQ    AT_SERDES_FLD_DEF(0x563C, 30, 30)
#define F_AT56G_MCU_REMOTE_REQ_FM AT_SERDES_FLD_DEF(0x563C, 29, 29)    /* MCU_REMOTE_REQ_FM_REG_LANE */
#define F_AT56G_MCU_REMOTE_REQ_RD AT_SERDES_FLD_DEF(0x561C, 31, 31)    /* PIN_MCU_REMOTE_REQ_RD_LANE */
#define F_AT56G_MCU_LOCAL_ACK     AT_SERDES_FLD_DEF(0x3530, 16, 16)
#define F_AT56G_MCU_LOCAL_STATUS  AT_SERDES_FLD_DEF(0x3534, 31, 0)

#define F_AT56G_PTN_LOCK_LOST_TO  AT_SERDES_FLD_DEF(0x5014, 24, 24)    /* PATTERN_LOCK_LOST_TIMEOUT_EN_LANE */
#define F_AT56G_TRX_TRAIN_TO_EN   AT_SERDES_FLD_DEF(0x5014, 10, 10)    /* TRX_TRAIN_TIMEOUT_EN_LANE */
#define F_AT56G_PLL_SEL_LANE      AT_SERDES_FLD_DEF(0x607c, 9, 8)      /* PLL_SEL_LANE */

/* SERDES Speeds */
typedef enum
{
    AT56G_SERDES_1P0625G      = 0,    /* 1.0625 Gbps*/
    AT56G_SERDES_1P2288G      = 1,    /* 1.2288 Gbps */
    AT56G_SERDES_1P25G        = 2,    /* 1.25 Gbps */
    AT56G_SERDES_2P02752G     = 50,   /* 2.02752 Gbps */
    AT56G_SERDES_2P125G       = 3,    /* 2.125 Gbps */
    AT56G_SERDES_2P4576G      = 4,    /* 2.4576 Gbps */
    AT56G_SERDES_2P5G         = 5,    /* 2.5 Gbps */
    AT56G_SERDES_2P57812G     = 46,   /* 2.578125 Gbps */
    AT56G_SERDES_3P125G       = 6,    /* 3.125 Gbps */
    AT56G_SERDES_4P08804G     = 51,   /* 4.08804 Gbps */
    AT56G_SERDES_4P25G        = 7,    /* 4.25 Gbps */
    AT56G_SERDES_4P9152G      = 8,    /* 4.9152 Gbps */
    AT56G_SERDES_5G           = 9,    /* 5 Gbps */
    AT56G_SERDES_5P15625G     = 10,   /* 5.15625 Gbps */
    AT56G_SERDES_6P144G       = 11,   /* 6.144 Gbps */
    AT56G_SERDES_6P25G        = 12,   /* 6.25 Gbps */
    AT56G_SERDES_7P3728G      = 52,   /* 7.3728 Gbps */
    AT56G_SERDES_7P5G         = 13,   /* 7.5 Gbps */
    AT56G_SERDES_8P11008G     = 53,   /* 8.11008 Gbps */
    AT56G_SERDES_8P5G         = 14,   /* 8.5 Gbps*/
    AT56G_SERDES_9P8304G      = 15,   /* 9.8304 Gbps */
    AT56G_SERDES_10G          = 49,   /* 10 Gbps */
    AT56G_SERDES_10P137G      = 16,   /* 10.137 Gbps */
    AT56G_SERDES_10P3125G     = 17,   /* 10.3125 Gbps */
    AT56G_SERDES_10P5187G     = 18,   /* 10.51875 Gbps */
    AT56G_SERDES_12P1651G     = 19,   /* 12.16512 Gbps */
    AT56G_SERDES_12P1875G     = 20,   /* 12.1875 Gbps */
    AT56G_SERDES_12P5G        = 21,   /* 12.5 Gbps */
    AT56G_SERDES_12P8906G     = 22,   /* 12.8906 Gbps */
    AT56G_SERDES_14P025G      = 23,   /* 14.025 Gbps */
    AT56G_SERDES_14P7456G     = 54,   /* 14.7456 Gbps */
    AT56G_SERDES_15G          = 47,   /* 15 Gbps */
    AT56G_SERDES_16P2201G     = 55,   /* 16.22016 Gbps */
    AT56G_SERDES_20P625G      = 24,   /* 20.625 Gbps */
    AT56G_SERDES_24P3302G     = 25,   /* 24.33024 Gbps */
    AT56G_SERDES_25P7812G     = 26,   /* 25.78125 Gbps */
    AT56G_SERDES_26P5625G     = 27,   /* 26.5625 Gbps */
    AT56G_SERDES_275G         = 28,   /* 27.5 Gbps*/
    AT56G_SERDES_28P05G       = 29,   /* 28.05 Gbps */
    AT56G_SERDES_28P125G      = 30,   /* 28.125 Gbps */
    AT56G_SERDES_32G          = 48,   /* 32 Gbps */
    AT56G_SERDES_46P25G       = 32,   /* 46.25 Gbps */
    AT56G_SERDES_51P5625G     = 34,   /* 51.5625 Gbps */
    AT56G_SERDES_53P125G      = 35,   /* 53.125 Gbps */
    AT56G_SERDES_56G          = 42,   /* 56 Gbps */
    AT56G_SERDES_56P1G        = 37,   /* 56.1 Gbps */
    AT56G_SERDES_56P25G       = 38,   /* 56.25 Gbps */
    AT56G_SERDES_64G          = 56,   /* 64G (R1.2+ only) */
    AT56G_SERDES_3P072G       = 57,   /* 3.072G (R1.2+ only) */
    AT56G_SERDES_12P288G      = 58,   /* 12.288G (R1.2+ only) */
    AT56G_SERDES_19P6608G     = 59,   /* 19.6608G (R1.2+ only) */
    AT56G_SERDES_11P40625G    = 64,   /* 11.40625 Gbps */
    AT56G_SERDES_10P9375G     = 65,   /* 10.9375 Gbps */
    AT56G_SERDES_12P96875G    = 63,   /* 12.96875 Gbps */
    AT56G_SERDES_27P34375G    = 62,   /* 27.34375 Gbps */
    AT56G_SERDES_27P78125G    = 61,   /* 27.78125 Gbps */
    
    AT56G_SERDES_MAX_G        = 255   /* invalid */
} _sys_at_serdes_56g_speed_e;

/* Reference Frequency Clock */
typedef enum
{
    AT56G_REFFREQ_25MHZ       = 0,    /* 25 MHz */
    AT56G_REFFREQ_30MHZ       = 1,    /* 30 MHz */
    AT56G_REFFREQ_40MHZ       = 2,    /* 40 MHz */
    AT56G_REFFREQ_50MHZ       = 3,    /* 50 MHz */
    AT56G_REFFREQ_62P5MHZ     = 4,    /* 62.5 MHz */
    AT56G_REFFREQ_100MHZ      = 5,    /* 100 MHz */
    AT56G_REFFREQ_125MHZ      = 6,    /* 125 MHz */
    AT56G_REFFREQ_156MHZ      = 7,    /* 156.25 MHz */
    AT56G_REFFREQ_122MHZ      = 8,    /* 122.88 MHz */
} _sys_at_serdes_56g_reffreq_e;

/* TX and RX Data Bus Width */
typedef enum
{
    AT56G_DATABUS_32BIT       = 0,
    AT56G_DATABUS_40BIT       = 1,
    AT56G_DATABUS_64BIT       = 2,
    AT56G_DATABUS_80BIT       = 3
} _sys_at_serdes_56g_data_width_e;

/* Data Path */
typedef enum
{
    AT56G_PATH_NEAR_END_LB    = 0,
    AT56G_PATH_LOCAL_LB       = 1,
    AT56G_PATH_EXTERNAL       = 2,
    AT56G_PATH_FAR_END_LB     = 3
} _sys_at_serdes_56g_path_e;

/* Hardware Pins */
typedef enum
{
    AT56G_PIN_RESET           = 0,
    AT56G_PIN_ISOLATION       = 1,    /* PIN_ISOLATION_ENB */
    AT56G_PIN_BG_RDY          = 2,
    AT56G_PIN_SIF_SEL         = 3,
    AT56G_PIN_MCU_CLK         = 4,
    AT56G_PIN_DIRECTACCES     = 5,    /* PIN_DIRECT_ACCESS_EN */
    AT56G_PIN_PHY_MODE        = 6,
    AT56G_PIN_REFCLK_TX0      = 7,    /* PIN_REFCLK_SEL_TX0 */
    AT56G_PIN_REFCLK_TX1      = 8,    /* PIN_REFCLK_SEL_TX1 */
    AT56G_PIN_REFCLK_TX2      = 9,    /* PIN_REFCLK_SEL_TX2 */
    AT56G_PIN_REFCLK_TX3      = 10,   /* PIN_REFCLK_SEL_TX3 */
    AT56G_PIN_REFCLK_RX0      = 11,   /* PIN_REFCLK_SEL_RX0 */
    AT56G_PIN_REFCLK_RX1      = 12,   /* PIN_REFCLK_SEL_RX1 */
    AT56G_PIN_REFCLK_RX2      = 13,   /* PIN_REFCLK_SEL_RX2 */
    AT56G_PIN_REFCLK_RX3      = 14,   /* PIN_REFCLK_SEL_RX3 */
    AT56G_PIN_REFFREF_TX0     = 15,   /* PIN_REF_FREF_SEL_TX0 */
    AT56G_PIN_REFFREF_TX1     = 16,   /* PIN_REF_FREF_SEL_TX1 */
    AT56G_PIN_REFFREF_TX2     = 17,   /* PIN_REF_FREF_SEL_TX2 */
    AT56G_PIN_REFFREF_TX3     = 18,   /* PIN_REF_FREF_SEL_TX3 */
    AT56G_PIN_REFFREF_RX0     = 19,   /* PIN_REF_FREF_SEL_RX0 */
    AT56G_PIN_REFFREF_RX1     = 20,   /* PIN_REF_FREF_SEL_RX1 */
    AT56G_PIN_REFFREF_RX2     = 21,   /* PIN_REF_FREF_SEL_RX2 */
    AT56G_PIN_REFFREF_RX3     = 22,   /* PIN_REF_FREF_SEL_RX3 */
    AT56G_PIN_PHY_GEN_TX0     = 23,
    AT56G_PIN_PHY_GEN_TX1     = 24,
    AT56G_PIN_PHY_GEN_TX2     = 25,
    AT56G_PIN_PHY_GEN_TX3     = 26,
    AT56G_PIN_PHY_GEN_RX0     = 27,
    AT56G_PIN_PHY_GEN_RX1     = 28,
    AT56G_PIN_PHY_GEN_RX2     = 29,
    AT56G_PIN_PHY_GEN_RX3     = 30,
    AT56G_PIN_PU_PLL0         = 31,
    AT56G_PIN_PU_PLL1         = 32,
    AT56G_PIN_PU_PLL2         = 33,
    AT56G_PIN_PU_PLL3         = 34,
    AT56G_PIN_PU_RX0          = 35,
    AT56G_PIN_PU_RX1          = 36,
    AT56G_PIN_PU_RX2          = 37,
    AT56G_PIN_PU_RX3          = 38,
    AT56G_PIN_PU_TX0          = 39,
    AT56G_PIN_PU_TX1          = 40,
    AT56G_PIN_PU_TX2          = 41,
    AT56G_PIN_PU_TX3          = 42,
    AT56G_PIN_TX_IDLE0        = 43,
    AT56G_PIN_TX_IDLE1        = 44,
    AT56G_PIN_TX_IDLE2        = 45,
    AT56G_PIN_TX_IDLE3        = 46,
    AT56G_PIN_PU_IVREF        = 47,
    AT56G_PIN_RX_TRAINEN0     = 48,   /* PIN_RX_TRAIN_ENABLE0 */
    AT56G_PIN_RX_TRAINEN1     = 49,   /* PIN_RX_TRAIN_ENABLE1 */
    AT56G_PIN_RX_TRAINEN2     = 50,   /* PIN_RX_TRAIN_ENABLE2 */
    AT56G_PIN_RX_TRAINEN3     = 51,   /* PIN_RX_TRAIN_ENABLE3 */
    AT56G_PIN_RX_TRAINCO0     = 52,   /* PIN_RX_TRAIN_COMPLETE0 */
    AT56G_PIN_RX_TRAINCO1     = 53,   /* PIN_RX_TRAIN_COMPLETE1 */
    AT56G_PIN_RX_TRAINCO2     = 54,   /* PIN_RX_TRAIN_COMPLETE2 */
    AT56G_PIN_RX_TRAINCO3     = 55,   /* PIN_RX_TRAIN_COMPLETE3 */
    AT56G_PIN_RX_TRAINFA0     = 56,   /* PIN_RX_TRAIN_FAILED0 */
    AT56G_PIN_RX_TRAINFA1     = 57,   /* PIN_RX_TRAIN_FAILED1 */
    AT56G_PIN_RX_TRAINFA2     = 58,   /* PIN_RX_TRAIN_FAILED2 */
    AT56G_PIN_RX_TRAINFA3     = 59,   /* PIN_RX_TRAIN_FAILED3 */
    AT56G_PIN_TX_TRAINEN0     = 60,   /* PIN_TX_TRAIN_ENABLE0 */
    AT56G_PIN_TX_TRAINEN1     = 61,   /* PIN_TX_TRAIN_ENABLE1 */
    AT56G_PIN_TX_TRAINEN2     = 62,   /* PIN_TX_TRAIN_ENABLE2 */
    AT56G_PIN_TX_TRAINEN3     = 63,   /* PIN_TX_TRAIN_ENABLE3 */
    AT56G_PIN_TX_TRAINCO0     = 64,   /* PIN_TX_TRAIN_COMPLETE0 */
    AT56G_PIN_TX_TRAINCO1     = 65,   /* PIN_TX_TRAIN_COMPLETE1 */
    AT56G_PIN_TX_TRAINCO2     = 66,   /* PIN_TX_TRAIN_COMPLETE2 */
    AT56G_PIN_TX_TRAINCO3     = 67,   /* PIN_TX_TRAIN_COMPLETE3 */
    AT56G_PIN_TX_TRAINFA0     = 68,   /* PIN_TX_TRAIN_FAILED0 */
    AT56G_PIN_TX_TRAINFA1     = 69,   /* PIN_TX_TRAIN_FAILED1 */
    AT56G_PIN_TX_TRAINFA2     = 70,   /* PIN_TX_TRAIN_FAILED2 */
    AT56G_PIN_TX_TRAINFA3     = 71,   /* PIN_TX_TRAIN_FAILED3 */
    AT56G_PIN_SQ_DET_LPF0     = 72,   /* PIN_SQ_DETECTED_LPF0 */
    AT56G_PIN_SQ_DET_LPF1     = 73,   /* PIN_SQ_DETECTED_LPF1 */
    AT56G_PIN_SQ_DET_LPF2     = 74,   /* PIN_SQ_DETECTED_LPF2 */
    AT56G_PIN_SQ_DET_LPF3     = 75,   /* PIN_SQ_DETECTED_LPF3 */
    AT56G_PIN_RX_INIT0        = 76,
    AT56G_PIN_RX_INIT1        = 77,
    AT56G_PIN_RX_INIT2        = 78,
    AT56G_PIN_RX_INIT3        = 79,
    AT56G_PIN_RX_INITDON0     = 80,   /* PIN_RX_INIT_DONE0 */
    AT56G_PIN_RX_INITDON1     = 81,   /* PIN_RX_INIT_DONE1 */
    AT56G_PIN_RX_INITDON2     = 82,   /* PIN_RX_INIT_DONE2 */
    AT56G_PIN_RX_INITDON3     = 83,   /* PIN_RX_INIT_DONE3 */
    AT56G_PIN_AVDD_SEL        = 84,
    AT56G_PIN_SPD_CFG         = 85,
    AT56G_PIN_PIPE_SEL        = 86,
    AT56G_PIN_PRAM_RESET      = 87,   /*HssPramCfg, cfgPramReset*/
    AT56G_PIN_PRAM_SOC_EN     = 88,   /**/
    AT56G_PIN_TX_RST0         = 90,   /*HssCmnCfg, cfgHssTxRstLane0*/
    AT56G_PIN_TX_RST1         = 91,   /*HssCmnCfg, cfgHssTxRstLane1*/
    AT56G_PIN_TX_RST2         = 92,   /*HssCmnCfg, cfgHssTxRstLane2*/
    AT56G_PIN_TX_RST3         = 93,   /*HssCmnCfg, cfgHssTxRstLane3*/
    AT56G_PIN_RX_RST0         = 94,   /*HssCmnCfg, cfgHssRxRstLane0*/
    AT56G_PIN_RX_RST1         = 95,   /*HssCmnCfg, cfgHssRxRstLane1*/
    AT56G_PIN_RX_RST2         = 96,   /*HssCmnCfg, cfgHssRxRstLane2*/
    AT56G_PIN_RX_RST3         = 97,   /*HssCmnCfg, cfgHssRxRstLane3*/
    AT56G_PIN_FW_READY        = 98,   /*HssCmnCfg, cfgHssFwReady*/
    AT56G_PIN_PLL_RDY_RX0     = 99,   /*HssMon, monHssPllReadyRxLane0*/
    AT56G_PIN_PLL_RDY_RX1     = 100,   /*HssMon, monHssPllReadyRxLane1*/
    AT56G_PIN_PLL_RDY_RX2     = 101,   /*HssMon, monHssPllReadyRxLane2*/
    AT56G_PIN_PLL_RDY_RX3     = 102,   /*HssMon, monHssPllReadyRxLane3*/
    AT56G_PIN_PLL_RDY_TX0     = 103,   /*HssMon, monHssPllReadyTxLane0*/
    AT56G_PIN_PLL_RDY_TX1     = 104,   /*HssMon, monHssPllReadyTxLane1*/
    AT56G_PIN_PLL_RDY_TX2     = 105,   /*HssMon, monHssPllReadyTxLane2*/
    AT56G_PIN_PLL_RDY_TX3     = 106,   /*HssMon, monHssPllReadyTxLane3*/
    AT56G_PIN_TX_RST_ACK0     = 107,   /*HssMon, monHssTxRstAckLane0*/
    AT56G_PIN_TX_RST_ACK1     = 108,   /*HssMon, monHssTxRstAckLane1*/
    AT56G_PIN_TX_RST_ACK2     = 109,   /*HssMon, monHssTxRstAckLane2*/
    AT56G_PIN_TX_RST_ACK3     = 110,   /*HssMon, monHssTxRstAckLane3*/
    AT56G_PIN_RX_RST_ACK0     = 111,   /*HssMon, monHssRxRstAckLane0*/
    AT56G_PIN_RX_RST_ACK1     = 112,   /*HssMon, monHssRxRstAckLane1*/
    AT56G_PIN_RX_RST_ACK2     = 113,   /*HssMon, monHssRxRstAckLane2*/
    AT56G_PIN_RX_RST_ACK3     = 114,   /*HssMon, monHssRxRstAckLane3*/
    AT56G_PIN_RX_GRAYCODE_EN0  = 115,   /*HssRxCfg, cfgHssRxGrayCodeEnLane0*/
    AT56G_PIN_RX_GRAYCODE_EN1  = 116,   /*HssRxCfg, cfgHssRxGrayCodeEnLane1*/
    AT56G_PIN_RX_GRAYCODE_EN2  = 117,   /*HssRxCfg, cfgHssRxGrayCodeEnLane2*/
    AT56G_PIN_RX_GRAYCODE_EN3  = 118,   /*HssRxCfg, cfgHssRxGrayCodeEnLane3*/
    AT56G_PIN_TX_GRAYCODE_EN0  = 119,   /*HssTxCfg, cfgHssTxGrayCodeEnLane0*/
    AT56G_PIN_TX_GRAYCODE_EN1  = 120,   /*HssTxCfg, cfgHssTxGrayCodeEnLane1*/
    AT56G_PIN_TX_GRAYCODE_EN2  = 121,   /*HssTxCfg, cfgHssTxGrayCodeEnLane2*/
    AT56G_PIN_TX_GRAYCODE_EN3  = 122,   /*HssTxCfg, cfgHssTxGrayCodeEnLane3*/
    AT56G_PIN_RX_PRECODE_EN0  = 123,   /*HssRxCfg, cfgHssRxPreCodeEnLane0*/
    AT56G_PIN_RX_PRECODE_EN1  = 124,   /*HssRxCfg, cfgHssRxPreCodeEnLane1*/
    AT56G_PIN_RX_PRECODE_EN2  = 125,   /*HssRxCfg, cfgHssRxPreCodeEnLane2*/
    AT56G_PIN_RX_PRECODE_EN3  = 126,   /*HssRxCfg, cfgHssRxPreCodeEnLane3*/
    AT56G_PIN_TX_PRECODE_EN0  = 127,   /*HssTxCfg, cfgHssTxPreCodeEnLane0*/
    AT56G_PIN_TX_PRECODE_EN1  = 128,   /*HssTxCfg, cfgHssTxPreCodeEnLane1*/
    AT56G_PIN_TX_PRECODE_EN2  = 129,   /*HssTxCfg, cfgHssTxPreCodeEnLane2*/
    AT56G_PIN_TX_PRECODE_EN3  = 130,   /*HssTxCfg, cfgHssTxPreCodeEnLane3*/
    AT56G_PIN_FORCE_PMA_RDY_EN0  = 131,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    AT56G_PIN_FORCE_PMA_RDY_EN1  = 132,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    AT56G_PIN_FORCE_PMA_RDY_EN2  = 133,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    AT56G_PIN_FORCE_PMA_RDY_EN3  = 134,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    AT56G_PIN_FORCE_PMA_RDY_VAL0  = 135,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    AT56G_PIN_FORCE_PMA_RDY_VAL1  = 136,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    AT56G_PIN_FORCE_PMA_RDY_VAL2  = 137,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    AT56G_PIN_FORCE_PMA_RDY_VAL3  = 138,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    AT56G_PIN_PRAM_CHECKSUM_RESET = 139,   /*HssPramCfg, cfgPramChecksumReset*/
    AT56G_PIN_PRAM_CHECKSUM       = 140,   /*HssPramMon, monPramChecksum*/
    AT56G_PIN_RX_DTL_CLAMP0       = 141,   /*HssMon, monHssRxDtlClampLane0*/         
    AT56G_PIN_RX_DTL_CLAMP1       = 142,   /*HssMon, monHssRxDtlClampLane1*/
    AT56G_PIN_RX_DTL_CLAMP2       = 143,   /*HssMon, monHssRxDtlClampLane2*/
    AT56G_PIN_RX_DTL_CLAMP3       = 144,   /*HssMon, monHssRxDtlClampLane3*/
    AT56G_PIN_PRAM_CHECKSUM_EN    = 145,   /*HssPramCfg, cfgPramChecksumEn*/
    AT56G_PIN_PRAM_CHECKSUM_SEL   = 146,   /*HssPramCfg, cfgPramChecksumSel*/
    AT56G_PIN_MCU_INIT_DONE       = 147,   /*HssMcuMon, monHssMcuInitDone*/
    
} _sys_at_serdes_56g_pin_e;

/* AVDD Select */
typedef enum
{
    AT56G_AVDD_1P1V           = 0x5,
    AT56G_AVDD_1P15V          = 0x6,
    AT56G_AVDD_1P2V           = 0x7
} _sys_at_serdes_56g_avdd_e;

/* Speed Configuration */
typedef enum
{
    AT56G_SPD_CFG_4_PLL       = 0x2,
    AT56G_SPD_CFG_ONLY_TS     = 0x3
} _sys_at_serdes_56g_spd_cfg_e;


/* Reference Clock selection Group */
typedef enum
{
    AT56G_REFCLK_SEL_G1       = 0,    /* PIN_REFCLKC_IN_SIDE_A_G1 or PIN_REFCLKC_IN_SIDE_B_G1 */
    AT56G_REFCLK_SEL_G2       = 1     /* PIN_REFCLKC_IN_SIDE_A_G2 or PIN_REFCLKC_IN_SIDE_B_G2 */
} _sys_at_serdes_56g_refclk_sel_e;


/*56G macro define end*/

/* Pattern selection */
typedef enum
{
    AT_SERDES_PAT_USER            = 0x0,
    AT_SERDES_PAT_PACKET          = 0x3,
    AT_SERDES_PAT_SSPRQ           = 0x4,
    AT_SERDES_PAT_JITTERK28P5     = 0x8,
    AT_SERDES_PAT_JITTER_1T       = 0x9,
    AT_SERDES_PAT_JITTER_2T       = 0xA,
    AT_SERDES_PAT_JITTER_4T       = 0xB,
    AT_SERDES_PAT_JITTER_5T       = 0xC,
    AT_SERDES_PAT_JITTER_8T       = 0xD,
    AT_SERDES_PAT_JITTER_10T      = 0xE,
    AT_SERDES_PAT_PRBS7           = 0x10,
    AT_SERDES_PAT_PRBS9           = 0x11,
    AT_SERDES_PAT_PRBS11          = 0x12,
    AT_SERDES_PAT_PRBS11_0        = 0x13,
    AT_SERDES_PAT_PRBS11_1        = 0x14,
    AT_SERDES_PAT_PRBS11_2        = 0x15,
    AT_SERDES_PAT_PRBS11_3        = 0x16,
    AT_SERDES_PAT_PRBS15          = 0x17,
    AT_SERDES_PAT_PRBS16          = 0x18,
    AT_SERDES_PAT_PRBS23          = 0x19,
    AT_SERDES_PAT_PRBS31          = 0x1A,
    AT_SERDES_PAT_PRBS32          = 0x1B,
    AT_SERDES_PAT_PRBS13_0        = 0x1C,
    AT_SERDES_PAT_PRBS13_1        = 0x1D,
    AT_SERDES_PAT_PRBS13_2        = 0x1E,
    AT_SERDES_PAT_PRBS13_3        = 0x1F,
} _sys_at_serdes_pattern_sel_e;

typedef enum _sys_at_cpumac_serdes_mode_e
{
    AT_CPUMAC_SERDES_SGMII_MODE,
    AT_CPUMAC_SERDES_2DOT5G_MODE,
    AT_CPUMAC_SERDES_XFI_MODE,
    AT_CPUMAC_SERDES_XXVG_MODE,
    AT_CPUMAC_SERDES_MAX_MODE
}_sys_at_cpumac_serdes_mode_t;

#define AT_IS_SERDES_SPEED_PAM4(serdes_speed)   ((serdes_speed == SERDES_SPEED_51_5625G || serdes_speed == SERDES_SPEED_53_125G  ||\
                                                  serdes_speed == SERDES_SPEED_56_25G   || serdes_speed == SERDES_SPEED_106_25G  ||\
                                                  serdes_speed == SERDES_SPEED_112_5G   || serdes_speed == SERDES_SPEED_56_25G   ||\
                                                  serdes_speed == SERDES_SPEED_42_5G) ? TRUE : FALSE)

#define AT_PHYMODE_SERDES 4
#define AT_SERDES_GET_LANE(serdes_id) (SYS_AT_IS_CPUMAC_SERDES(serdes_id) ? (serdes_id % AT_CPUMAC_PER_CORE) : (serdes_id % AT_SERDES_NUM_PER_HSS))
#define AT_SERDES_GET_GROUP_PER_CORE(serdes_id) (SYS_AT_IS_CPUMAC_SERDES(serdes_id) ? 40 : (serdes_id % SYS_AT_NW_SERDES_NUM_PER_CORE / AT_SERDES_NUM_PER_HSS))
#define AT_SERDES_GROUP_NUM_PER_CORE ((SYS_AT_NW_SERDES_NUM_PER_CORE+AT_SERDES_NUM_PER_HSS)/AT_SERDES_NUM_PER_HSS)
#define AT_SERDES_CPUMAC_GROUP 40
#define AT_BER_IF_FACTOR     10000
#define AT_GET_BER(bit_cnt, bit_err_cnt)     (uint32)((AT_BER_IF_FACTOR * (uint64)bit_err_cnt) / ((uint64)bit_cnt))
#define AT_GET_BER_LEVEL(bit_cnt, bit_err_cnt, level) \
    do\
    {\
        uint32 ber = AT_GET_BER(bit_cnt, bit_err_cnt);\
        if(0 == ber)            level = 0;    /*BER = 0*/\
        else if(10 >= ber)      level = 1;    /*BER <= 1E-3*/\
        else if(1000 >= ber)    level = 2;    /*BER <= 1E-1*/\
        else                    level = 255;  /*BER > 1E-1*/\
    }\
    while(0)
#define AT_TXFFE_UVAL_MAX  127
#define AT_FFE_SIGN_BIT  16
#define AT_FFE_MASK      0xFFFF

/*FIELD_DEFINE*/
#define AT_SERDES_FLD_DEF(reg, hi_bit, lo_bit) { \
    reg, \
    hi_bit, \
    lo_bit, \
    (hi_bit-lo_bit) + 1, \
    (uint32) ((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit), \
    (uint32) ~((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit)}

/*EXTRACT_FIELD*/
#define AT_SERDES_FLD(xFIELD) { \
    xFIELD.reg, \
    xFIELD.hi_bit, \
    xFIELD.lo_bit, \
    xFIELD.total_bits, \
    xFIELD.mask, \
    xFIELD.retain_mask}

struct _sys_at_serdes_field_s
{
    uint32 reg;
    int16  hi_bit;
    int16  lo_bit;
    int16  total_bits;
    uint32 mask;
    uint32 retain_mask;
};
typedef struct _sys_at_serdes_field_s _sys_at_serdes_field_t;
#define REG_STR(FLD_DEF) (&(_sys_at_serdes_field_t)FLD_DEF)

struct sys_at_serdes_dev_s
{
    uint16 serdes_id;
    uint8 lchip;
    uint8 type; /*sys_at_serdes_type_t*/
};
typedef struct sys_at_serdes_dev_s sys_at_serdes_dev_t;

typedef struct
{
    uint16 serdes_id;
    uint8  is_tx_en;
    uint8  is_load_fw;
    
    uint8  ref_clk_sel;
    uint8  ref_freq;
    uint8  data_width;
    uint8  txrx_speed;
    
    uint8  avdd;
    uint8  spd_cfg;
} sys_at_serdes_power_on_t;

typedef enum
{
    SYS_AT_SERDES_REG_LANE,
    SYS_AT_SERDES_REG_GRP,
    SYS_AT_SERDES_REG_BUTT
}_sys_at_serdes_reg_type_e;

typedef enum
{
    SYS_EYE_HEIGHT,
    SYS_EYE_WIDTH,
    SYS_EYE_BUTT
}_sys_at_serdes_eye_e;

typedef enum
{
    SYS_EYE_PAM4_MID,
    SYS_EYE_PAM4_TOP,
    SYS_EYE_PAM4_BOT,
    SYS_EYE_PAM4_TMB_BUTT
}_sys_at_serdes_eye_pam4_tmb_e;

/* Eye Measurement Data @ X,Y and X,-Y */
typedef struct
{
    int32 phase;
    uint8 voltage;
    uint64 bit_cnt_u;
    uint32 be_cnt_u;
    uint64 bit_cnt_l;
    uint32 be_cnt_l;
} _sys_at_serdes_eye_meas_data_t;

typedef enum
{
    SYS_MSBLSB_MODE_DISABLE,
    SYS_MSBLSB_MODE_PRECODER,
    SYS_MSBLSB_MODE_POSTCODER,
    SYS_MSBLSB_MODE_BUTT,
}_sys_at_serdes_msblsb_mode_e;

typedef enum
{
    RX_NO_SIGNAL,       /*sigdet = 0*/
    RX_VALID_SIGNAL,    /*sigdet = 1 && CDR lock*/
    RX_INVALID_SIGNAL,  /*sigdet = 1 && CDR unlock*/
}_sys_at_serdes_signal_valid_e;

typedef enum
{
    SYS_AT_SERDES_FW_DEFAULT = 0,   /*download default firmware = 0*/
    SYS_AT_SERDES_FW_DEBUG = 1,     /*download debug firmware = 1*/
    SYS_AT_SERDES_FW_MAX,
}_sys_at_serdes_download_fw_flag_e;

#ifdef __cplusplus
}
#endif


int32 sys_at_serdes_init(uint8 lchip);
int32 _sys_at_serdes_set_loopback(uint8 lchip, void* p_data);
int32 _sys_at_serdes_get_loopback(uint8 lchip, void* p_data);
void _sys_at_serdes_to_dev(uint8 lchip, uint16 serdes_id, uint8 type, sys_at_serdes_dev_t* p_dev);
int32 _sys_at_serdes_read_reg_field(sys_at_serdes_dev_t* p_dev, _sys_at_serdes_field_t* p_field, 
                                               uint8 reg_type, uint32* p_data);
int32 _sys_at_serdes_write_reg_field(sys_at_serdes_dev_t* p_dev, _sys_at_serdes_field_t* p_field, 
                                                uint8 reg_type, uint32 data);
int32 _sys_at_serdes_poll_reg_field(sys_at_serdes_dev_t* p_dev, _sys_at_serdes_field_t* p_field, 
                                                uint8 reg_type, uint32 exp_value);
int32 _sys_at_serdes_get_pin(sys_at_serdes_dev_t* p_dev, uint16 pin, uint32 *value);
int32 _sys_at_serdes_set_pin(sys_at_serdes_dev_t* p_dev, uint16 pin, uint32 value);
int32 _sys_at_serdes_poll_pin(sys_at_serdes_dev_t* p_dev, uint16 pin, uint32 exp_value);
int32 _sys_at_serdes_get_signal_detect(uint8 lchip, uint16 psd, uint8* p_is_detect, uint8* p_raw_sigdet);
int32 _sys_at_serdes_get_cdr_lock(uint8 lchip, uint16 psd, uint32* p_lock);
void _sys_at_get_serdes_dev(uint8 lchip, uint16 serdes_id, sys_at_serdes_dev_t* p_dev);
int32 _sys_at_serdes_set_tx_en(sys_at_serdes_dev_t* p_dev, uint16 state);
int32 sys_at_serdes_get_link_training_status(uint8 lchip, uint16 serdes_id, uint16* p_value);
int32 sys_at_serdes_set_link_training_en(uint8 lchip, uint16 serdes_id, uint8 enable);
int32 _sys_at_serdes_set_rx_train_en(sys_at_serdes_dev_t* p_dev, uint16 en);
int32 _sys_at_serdes_get_rx_train_en(sys_at_serdes_dev_t* p_dev, uint32* p_train_en, uint32* p_train_co, uint32* p_train_fa);
int32 _sys_at_serdes_get_prbs_rx_enable(sys_at_serdes_dev_t* p_dev, uint32* p_en);
uint32 _sys_at_serdes_get_power_ivref(sys_at_serdes_dev_t* p_dev, uint32* p_state);
int32 _sys_at_serdes_get_lane_power(sys_at_serdes_dev_t* p_dev, uint32* p_pu_pll, uint32* p_pu_tx, uint32* p_pu_rx);
int32 _sys_at_serdes_get_snr(sys_at_serdes_dev_t* p_dev, uint32* snr_db);
int32 _sys_at_serdes_get_txrx_bit_rate(sys_at_serdes_dev_t* p_dev, uint32* p_tx_spd, uint32* p_rx_spd);
uint8 _sys_at_serdes_get_related_serdes_speed(uint8 txrx_speed, uint8 type);
int32 _sys_at_serdes_get_pll_tx_ready(sys_at_serdes_dev_t* p_dev, uint32* p_tx_rdy);
int32 _sys_at_serdes_get_signal_detect(uint8 lchip, uint16 psd, uint8* p_is_detect, uint8* p_raw_sigdet);
int32 _sys_at_serdes_get_pll_sel(sys_at_serdes_dev_t* p_dev, uint32* p_pll_sel);
int32 _sys_at_serdes_get_data_width(sys_at_serdes_dev_t* p_dev, uint16* p_txwidth, uint16* p_rxwidth);
int32 _sys_at_serdes_get_tx_en(sys_at_serdes_dev_t* p_dev, uint32* p_state);
int32 _sys_at_serdes_get_sq_thrd(sys_at_serdes_dev_t* p_dev, uint32* p_thrd);
int32 _sys_at_serdes_get_polarity(uint8 lchip, uint16 serdes_id, uint8 dir, uint16 *p_val);
int32 _sys_at_serdes_get_prbs_tx(sys_at_serdes_dev_t* p_dev, uint8* p_en, uint8* p_pattern);
int32 _sys_at_serdes_get_training_status(sys_at_serdes_dev_t* p_dev, uint16* p_status);
int32 _sys_at_serdes_get_training_en(sys_at_serdes_dev_t* p_dev, uint32* p_en);
int32 _sys_at_serdes_get_eye(uint8 lchip, void* p_data);
int32 _sys_at_serdes_get_txeq_param(uint8 lchip, ctc_chip_serdes_ffe_t* p_ffe);
int32 _sys_at_serdes_get_pll_rx_ready(sys_at_serdes_dev_t* p_dev, uint32* p_rx_rdy);
int32 _sys_at_serdes_get_dtl_clamp(uint8 lchip, uint16 psd, uint32* p_dtl_clp);



#endif

